Advanced Phase-Locked Loops
National Taiwan University
Department of Electrical Engineering
& Graduate Institute of Electronics Engineering
Issues in PLLs
Crystal Oscillator Lineairty
1. Low power Phase Noise, Supply noise,
Dead Zone Mismatching Area
2. Fast start-up, Tuning range, Gain,
Speed Leakage Variation
Low start-up energy LC or Ring VCO
High-Gain PFD Spur Leakage
MEMS Oscillator
Phase/Frequency Charge Loop
VCO
Detector Pump Filter
fref fout
CP LPF
Crystal
reference fd
Main divider
1
N
Area
Order Locking Range
Quantization Noise Power
Delta-Sigma Speed
Modulator
2 Electronic Circuits lab.
Low Noise PLLs
How to reduce the phase noise or jitters of PLLs in SOCs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
3 Electronic Circuits lab.
Multiplying Delay-Locked Loop (I)
Ring Oscillator MDLL
Noise is accumulated Accumulated Noise reduced
This is at least 2.5 higher than PLLs’
IEEE JSSC, pp. 1416-, June 2013
highest bandwidth (fREF/10).
ISSCC, Feb. 2012
4 Electronic Circuits lab.
Multiplying Delay-Locked Loop (II)
IEEE JSSC, pp. 1759-, Dec. 2002
IEEE JSSC, pp. 1804-, Dec. 2002
Recirculating DLL IEEE JSSC, pp. 1222-, Aug. 2004
5 Electronic Circuits lab.
Low Noise PLLs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
6 Electronic Circuits lab.
Noises in Fractional-N PLLs
7 Electronic Circuits lab.
Noises Vs. PLL’s Bandwidth
DS quantization noise will degrade the PN.
IEEE JSSC, pp. 2426-, Sep. 2009
8 Electronic Circuits lab.
FIR-Embedded Noise Filtering Method
IEEE JSSC, pp. 2426-, Sep. 2009
9 Electronic Circuits lab.
Noise Filtering in Wideband PLL
DS quantization noise multiplied by H(z)
10 Electronic Circuits lab.
PLL with FIR-Embedded Phase Interpolator
ISSCC, Feb. 2011
IEEE JSSC, pp.
DS quantization noise multiplied by an FIR filter 2795-, Sep. 2013
11 Electronic Circuits lab.
All-Digital FIR-Embedded Noise Filtering (I)
(7 z 1 z 2 z 3 z 4 z 5 z 6 z 7 )
D0 [k ] D0 [k ]
8
(1 z 1 z 2 z 3 z 4 z 5 z 6 z 7 )
D0 [k ]
8
IEEE T-CAS-II, pp. 267-, May 2012
12 Electronic Circuits lab.
All-Digital FIR-Embedded Noise Filtering (II)
Fref TR 2pKDCOTRz-1 Fout
DLF(z)
+ 2pDTDC 1-z-1
-
÷8
gT
1
Nnom +
-
2pz-1 z-1
1-z-1 1-z-1
D0[k] x7 - +
+ ++
z-1 z-1 z-1
1 2 7
H ( z) 2p z 1 1 1 2 3 4 5 6 7
F out D0 [k ] 1
(1 z z z z z z z )
1 H ( z) 1 z 8
13 Electronic Circuits lab.
Fractional-N PLL with a Noise Filter
Kd F(s) Kvco
REF PFD/CP VCO OUT
Rp Cs
Cp
Fb
Noise Filter Fb1 Multi-modulus Divider
HNF(s) (1/N)
Kvco,NF 3
Kd,NF
Fb Fb1 M Frequency
VCONF PFD/CP 3rd-order
Selection
RNF DSM
Cs,NF CNF
DS quantization noise multiplied by HNF(s)
IEEE T-CAS-II, pp. 139-, March 2011
14 Electronic Circuits lab.
Fractional-N PLL with a Nested PLL
• Feedback divider is split to increase the operating frequency of the DSM
• Suppress quantization noise
IEEE JSSC, pp. 2433-, Oct. 2012
15 Electronic Circuits lab.
Low Noise PLLs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
16 Electronic Circuits lab.
Sub-harmonically Injection-Locked Technique
Realigned PLL IEEE JSSC, pp. 1759-, Dec. 2002
IEEE JSSC, pp. 1539-, May 2009
IEEE TCAS-I, pp. 355-, Jan. 2019
17 Electronic Circuits lab.
Sub-harmonically Injection-Locked PLLs
Can it be automatically
controlled?
IEEE JSSC, pp. 1539-, May 2009
18 Electronic Circuits lab.
Injection Timing Issue
Electronic Circuits lab.
A PLL with Self-Calibrated Injection Timing
• Calibrate the CP current mismatch to educe the static phase error
• Calibrate the injection timing to tolerate the process variations
IEEE JSSC, pp. 417-, Feb. 2013
20 Electronic Circuits lab.
Replica VCO
To suppress the reference spur
IEEE JSSC, pp. 2989-, Dec. 2012
Electronic Circuits lab.
Dual-Pulse Ring Oscillator (DPRO) (I)
Even inverters --> the loop will not oscillate
DPRO is considered as perfect replica VCOs
Electronic Circuits lab.
Dual-Pulse Ring Oscillator (DPRO) (II)
IEEE JSSC, pp. 2989-, Dec. 2012
Electronic Circuits lab.
Low Noise PLLs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
24 Electronic Circuits lab.
Conceptual Sub-Sampling PD
IEEE JSSC, pp. 3253-, Dec. 2009
25 Electronic Circuits lab.
High-Gain Sub-Sampling PD
IEEE JSSC, pp. 3253-, Dec. 2009
26 Electronic Circuits lab.
A PLL Using A Sub-Sampling PD
Why low noise?
1. Dividerless in Locking
2. High-Gain PD
IEEE JSSC, pp. 3253-, Dec. 2009
27 Electronic Circuits lab.
An Injection-Locked PLL with Self-Aligned Injection (I)
ISSCC, pp.90-91, Feb. 2011
28 Electronic Circuits lab.
An Injection-Locked PLL with Self-Aligned Injection (II)
ISSCC, pp.90-91, Feb. 2011
29 Electronic Circuits lab.
An Injection-Locked PLL with Self-Aligned Injection (III)
Selected VCO architecture for injection
Defining b as the injection strength
0.83 < b < 0.91 in this work
30 Electronic Circuits lab.
Injection-Locked VCO with S/H PD
ISSCC, pp.90-91, Feb. 2011
31 Electronic Circuits lab.
Low Noise PLLs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
32 Electronic Circuits lab.
PLL Noise Analysis (I)
IEEE JSSC, pp. 2566-, Dec. 2010
33 Electronic Circuits lab.
PLL Noise Analysis (II)
Increasing Ipump reduces Input-Referred Loop Filter Noise, but
Open Loop Gain increases.
Area gets larger since C2 is typically increased to maintain
desired open loop gain
IEEE JSSC, pp. 2566-, Dec. 2010
34 Electronic Circuits lab.
PLL Noise Analysis (III)
But how do we increase the PD gain?
IEEE JSSC, pp. 2566-, Dec. 2010
35 Electronic Circuits lab.
Phase Gain of a Classical Tristate PFD
IEEE JSSC, pp. 2566-, Dec. 2010
36 Electronic Circuits lab.
High Gain Phase Detector
IEEE JSSC, pp. 2566-, Dec. 2010
37 Electronic Circuits lab.
A High-Gain PFD
IEEE JSSC, pp. 2566-, Dec. 2010
38 Electronic Circuits lab.
Phase-to-Voltage Converter
Phase-error pre-amplification to enable
reduction of PLL in-band phase noise floor
IEEE JSSC, pp. 2079-, Sept. 2008
39 Electronic Circuits lab.
Aperture Phase Detector
Aperture Phase Detector
IEEE TCAS-I, pp. 37-, Jan. 2013
40 Electronic Circuits lab.
Phase-to-Analog Converter
Phase-to-Analog
Converter
41 Electronic Circuits lab.
Low Noise PLLs
Several solutions
▉ Multiplying Delay-Locked Loop
▉ Noise filter: embedded FIR filter
▉ Sub-harmonically Injection-locked Technique
▉ Sub-sampling PD
▉ High-gain PFD
▉ Dual-Loop Hybrid Architecture
42 Electronic Circuits lab.
Dual-Loop Hybrid Architecture
ISSCC, Feb. 2006
43 Electronic Circuits lab.
Detail Circuit Block Diagram
ISSCC, Feb. 2006
44 Electronic Circuits lab.
Hybrid PLL Architecture
ISSCC, pp. 98-. Feb. 2011
45 Electronic Circuits lab.
Thee-input PFD
Should be
“ NAND”
ISSCC, pp. 98-. Feb. 2011
46 Electronic Circuits lab.
Dual-Tuning Architecture (I)
Pros: CP/LPF noise can be suppressed by integrator and
lowering fine-path gain KF. Coarse path achieves wide
tracking range.
Cons: Limitation of lowering KF because of stability.
ISSCC, pp. 248-, Feb. 2012
47 Electronic Circuits lab.
Dual-Tuning Architecture (II)
ISSCC, pp. 248-, Feb. 2012
48 Electronic Circuits lab.
Dual-Tuning Architecture (III)
ISSCC, pp. 248-, Feb. 2012
49 Electronic Circuits lab.
Dual-Tuning Architecture (IV)
ISSCC, pp. 248-, Feb. 2012
50 Electronic Circuits lab.
Design Constraint for Sufficient Stability
51 Electronic Circuits lab.
Digitally Stabilized DT-PLL
52 Electronic Circuits lab.
