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The document discusses the synchronization of a CPU clock with the bus clock (HCLK) by using latches at the interface. It emphasizes the importance of aligning the CPU clock's rising edge with HCLK and maintaining this relationship across various operating conditions. The approach includes strategies to handle early or late CPU clock signals to ensure data availability.

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Serajeldeen Ghalyoub 201-801-104
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14 views1 page

New Microsoft Word Document

The document discusses the synchronization of a CPU clock with the bus clock (HCLK) by using latches at the interface. It emphasizes the importance of aligning the CPU clock's rising edge with HCLK and maintaining this relationship across various operating conditions. The approach includes strategies to handle early or late CPU clock signals to ensure data availability.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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This approach requires a CPU clock that is always a multiple of the bus clock

(HCLK). We add latches at the interface between the CPU and the AMBA bus.
The CPU clock is adjusted so that its rising edge occurs roughly aligned to
the active (ris ing-edge) of bus clock HCLK With careful design, we can
maintain this relationship to within half a CPU clock period over all operating
conditions (including changing the voltage and clock frequency). We then
need to deal with the fact that the CPU clock can be early or late relative to
HCLK. To deal with the case of an early CPU clock, we over-constrain
synthesis to guarantee that data arrives early (by our worst case skew). If
the CPU clock is late, the latch assures that data is still available

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