Inverter design

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| CMD |
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csh
source /home/install/cshrc
virtuoso
file -> new -> library -> name -> attach to an existng lib -> select gpdk180
file -> new cellview -> select my lib -> cell name
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| inverter |
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create instance or I -> gpdk180 -> cell nmos -> hide
add pmos
create pin vin vdd vss direction (input)
paste vin vdd vss
create pin vout direction (output)
press w to connect wire
check and save to see error
go to create -> cellview -> from cellview -> ok -> assign pins (symbol creation)
delete outer box outer line , instance name -> portname replace with inverter
create triangle by pressing line and add circle to look like not gate
save check and save
file new file create (for testbech)
instance select my library (same library and same cell name)
select analog lib cell name v pulse click defaults v1 0 v2 2 timeperiod 100ns pulse with 50ns(half of time
period )
add vdc dc voltage 2
create pin vout direction output
add gnd
connect components using wire (w)
check and save
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| ADE L window |
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launch adel windows -> analysis -> trans -> stop time 100ns-> moderate
analysis -> dc -> save dc compontes -> select components parameter-> select dc start time 0 stop time 1 ok
outputs -> setup -> from design select input wire and output wire ok
run (green)
graph split all stipes to see input and output graph
launch -> layout xl -> create new -> ok
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| Connectivity window |
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connectivity -> generate -> all from source 0.12 -> select inboundary ok
shift F to see layout -> select vdd pin right click -> pin placement -> edge top -> apply -> hrail
select vss pin -> pin placement -> edge bottom -> apply -> hrail
press nmos and press q go to parameter body type integrater
press pmos and press q go to parameter body type integrater
press p metal 1 to vdd connect (ESC)
press p metal 1 to vss connect (ESC)
press p connect vout to vout (in mos)(ESC)
press p poly to poly
press p connect vout to vout (in end metal and vout line)
press p drag input line and press space bar select poly press some area and connect to poly
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| asoura |
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asura -> technology
click on ...
double click on .. (3 times)
install -> foundary -> analong -> 180nm -> asura tech .lib
click on asura runDRC -> runname DRC -> technology[-] gpgdk180 -> click on yes (for check errors)
asoura -> run lvs -> run namelvs -> ok
asoura -> run quantus -> output (extracted view)
extraction ->extraction type rc ->ref node vss -> goundsub[-] -> diable hrcx
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| command windows |
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command windows -> tools -> lib manager -> select project -> cell inverter -> double click on av extracter ->
shift f or ctrl f (rc extraction)
command windows -> tools -> lib manager -> select project -> select tb -> select schmatic -> file -> new
cellview -> type config -> ok
view ->scematic ->use template -> template -> spectre (all data) -> tree view -> io pins -> right click ->set
instance view -> av extraction (to see all data)
go to command window -> file -> import -> stream -> stream file (inverter.gds) ->lib working dir -> translate
->yes
file -> export -> stream -> stream file inv.gds -> lib working dir -> apply
go working dir -> search inv.gds -> open with text editor
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vending machine
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| cmd |
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csh
source /home/install/cshrc
nclaunch -new
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| compilation |
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select multiple steps c -> create cds file -> save -> don't include any lib
select vending machine.v -> launch with verilog compiler with current selection (compile)
select testbench.v -> launch with verilog compiler with current selection (compile)
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| elaboration |
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click work lib
launch elaboration with current selection
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| simulation |
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goto snapshot -> worklib.testbench .module-> launch simulation with current selection
select testbench -> send to waveform windows -> click on play button
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| xrun(xelium) |
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xrun filename.v testbench.v -access +rwc -gui (read and write connectivity)
select testbench -> send to waveform windows -> click on play button
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| Genus |
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copy file path (pwd)
open rcscript.tcl -> 2)set_db _hdl_search_path paste file loc || 6)read sdc paste file path
save
open in terminal
csh
source /home/install/cshrc
genus
source rcscript.tcl
click on + symbol in genus windows
click schematic
genus window -> timing -> debug timing ->ok
genus window -> report -> detailed power ->ok
file -> report -> gate count
goto genus command window -> report_power || report_timing || report_area
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| logic equivalence checking(LEC) |
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open lec command folder -> paste path (.v file) in 2) and 3) line
open terminal in that folder -> csh , source /home/install/cshrc
lec_auto
{ paste the first line (from lec file)-> in setup
paste the second line (from lec file) -> in setup
paste the thrid line (from lec file) -> in setup } -> for input and output check and some verification
setup -> lec
click on compare -> add all compare points
tools -> hdl tool manager (for check the rtl error)
tools -> mapping manager (to see the mapped points )
select chock out to see schematic for verilog and verilog checklist
golden - verilog schematic
revised - netlist schematic
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| innovus |
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csh
source /home/install/cshrc
innovus
file -> import design -> verilog -> click on ... -> arrow >> -> vending machine_ netlish.v add -> select lef
files -> click on ... -> arrow >> -> type /home/install/foundary/digital/90mm/dig/lef/ -> trasated two files
select -> power nets VDD ->ground nets VSS -> create analysis -> select library sets right click new -> type
slow -> add ->arrow symbol >> -> /home/install/foundary/digital/90mm/dig/lib/slow.lib ->close -> ok ->
select library sets right click new -> type fast -> add ->arrow symbol >> ->
/home/install/foundary/digital/90mm/dig/lib/fast.lib -> close -> ok ->rc corners -> right click new -> name Rc
-> cap table ...->/home/install/foundary/digital/90mm/dig/captable/select file -> same procedurce select qrc ->
delay corners select -> name max -> rc corner rc -> libset slow -> delay corners select -> name min -> rc
corner rc -> libset fast -> constraint mode -> new-> name constraint -> add -> vending machine_block_sdc
-> add -> close ->ok
analysis view -> name bc -> delay corners min -> analysis view -> name wc -> delay corners max -> setup
analysis best case(bc) -> hold analysis worst case (wc) -> save and close -> save -> save -> ok
goto -> floor plan -> specify floorplan -> rationhw 1 -> core utilization 0.7 -> core to die boundary set all
values 6 -> ok -> power -> connect golbal nets -> pin name VDD -> golbal nets VDD -> add to list -> pin
name vss -> global net name vss -> add to list -> power -> power planning -> add rings -> add VDD VSS in
file path -> top an bottom metal 9 (9)H -> left and right metal8(8) verical -> offset -> update -> ok
power -> power planning -> add stripes -> click on folder and VDD and VSS -> metal (9) horizantal update
-> number of sets 2 -> click on ok
power ->power planning -> add stripes ->click on folder and VDD and VSS -> metal (8) vertical update ->
number of sets 2 -> click on ok
route -> special route -> select folders -> ok
place -> physical cell -> add end cap -> fill 1 and fil2 respective boxes ->ok
place -> physical cell -> add well tap -> fill 1 and fill 2 -> add 30 in box
place -> standard cell -> mode ->placement -> place i/o pins -> ok -> ok
colck -> clock tree -> debugging -> ok
routing -> nano rounte -> route -> timing and si driven -> ok
timing -> debug timing ->ok
verify -> drc and connectivity
command windows -> zero violation and zero warning
right click on layout 3d -> current view (For 3d view)
click any layer to see its properties
on right side window disable layer -> tools -> schematic view
file -> save design -> innovus -> vendingmachine_router -> file -> save vendingmachince.gds
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