Mark Student's names Signature
Al-Kufa University
Engineering College
Electronic And Communication Department
3rd stage
LABORATORY MANUAL
Experiment 5
Asynchronous Counters
Prepared by:
Asst.lec. Muhiialdin M.ridha
2023-2024
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1. Aims:
Analyze and explain the operation of various circuits that is used to design
asynchronous counter.
2. Theory :
A Counter is a device which stores (and sometimes displays) the number of
times a particular event or process has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting purpose, they can count
specific event happening in the circuit.
2.1 Classification of counters:
2.1.1 According to clock connection:
Asynchronous (Ripple):
In asynchronous counter we don’t use universal clock, only first flip
flop is driven by main clock and the clock input of rest of the following flip
flop is driven by output of previous flip flops. It sometimes called ripple
counters because the data appears to “ripple” from the output of one flip-
flop to the input of the next. It can easily be made from Toggle or D-type
flip-flops.
Synchronous:
Unlike the asynchronous counter, synchronous counter has one
global clock which drives each flip flop so output changes in parallel.
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2.1.2 According to counter progress:
Up counter:- can be designed in two ways:
► Negative edge triggered: Q is the clock
► Positive edge triggered: is the clock
Down counter
► Negative edge triggered: is the clock
► Positive edge triggered: Q is the clock
To make down counter you can either connect the clk to Q' instead of Q or
use the same circuit of up counter and take the output from Q' instead of Q
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Up / Down counter (Bidirectional counter)
It is capable of counting in either the up direction or the down direction
through any given count sequence . Generally most bidirectional counter chips
can be made to change their count direction either up or down at any point
within their counting sequence. This is achieved by using an additional input
pin which determines the direction of the count, either Up or Down and the
timing diagram gives an example of the counters operation as this Up/Down
input changes state.
2.1.3 According to number of states:
► Fully states: counts from 0 to
► Decade counter (Partial states) (MOD counter)
3. Procedures:
3.1 Procedure 1:
1. Recognize the up counter circuits shown in section 2.1.2 and use the same
concept to connect 4 bits down counter. Draw the circuit diagram below.
Note to connect both clr and pre inputs to logic 1
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2. Draw the output results as waveforms on the figure below.
QA
QB
QC
QD
3.2 Procedure 2 :
1. Design 4 bits up/down asynchronous counter by filling the table first then
connect any combinational circuit you need to clk input. The counter counts up
when M = 0 and counts down when M = 1.
Flip flop
Output
M output
clk
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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2. Draw the circuit diagram of your design in the figure below.
4. Resources
https://www.geeksforgeeks.org/counters-in-digital-logic/?ref=lbp
