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Design of RS (255, 251) Encoder and Decoder in FPGA

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 International Journal of Soft Computing and Engineering (IJSCE)
ISSN: 2231-2307, Volume-2, Issue-6, January 2013

Design of RS (255, 251) Encoder and Decoder in

FPGA
Anindya Sundar Das, Satyajit Das and Jaydeb Bhaumik

Abstract— Detection and correction of errors in digital data is II. REED-SOLOMON CODES
an important issue for the modern communication systems.
Reed-Solomon codes are linear block codes and a subset of
Therefore an efficient error control code is needed to protect the
digital data. In high speed communication system Reed-Solomon BCH codes. An RS code is based on finite fields, often called
codes are widely used to provide error protection especially Galois fields. The number and types of errors that can be
against the burst errors. Reed-Solomon codes are cyclic, corrected depends on the characteristics of the
non-binary codes. In this paper RS(255, 251)encoder and decoder Reed-Solomon code. RS (n, k) codes parameters are
have been designed and implemented on an FPGA platform. described as follows.

Index Terms—Reed-Solomon codes, Galois field, RS encoder, m - Number of bits per symbol
RS decoder. k- Un-coded message length in symbols
n- Codeword length in symbols
I. INTRODUCTION (n-k)- Number of parity check symbols
t -Number of correctable symbol errors and 2t = n-k
Error correcting codes have a wide range of applications in
=

different fields like digital data communications, memory

Figure 1 shows a typical systematic Reed-Solomon
system design, and fault tolerant computer design among
codeword. It is systematic because the data on the left is
others. Reed-Solomon (RS) code is a well known non-binary
unchanged and the parity symbols are appended with data to
linear block code. It is popularly used for error correction in
form the code word.
many applications like storage devices (CD, DVD), wireless
communications, high speed modems and satellite
communications. For example RS (28, 24) and RS (32, 28)
codes with interleaving are popularly used for storage in CD.
A 16 bytes error correcting RS (255, 223) code has been
used for digital μ-wave radio. The code RS (255, 239) having
8 bytes error correcting capability has been recommended as Fig1: RS(n, k) Codeword
a outer code in WiMax. To preserve important header
information, MB-OFDM UWB adopts RS (23, 17) codes. An RS code with 8-bit symbols will use a Galois field
Basics of RS codes and a number of decoding techniques GF(28). For RS (255,251) code, n = block length = 255, k =
may be found in the literature [1] [2]. Several important no. of un-coded massage symbols= 251, 2t = (n-k) = number
applications of RS codes have been discussed in [3]. Parallel of parity symbols =4, t = maximum number of errors can be
architecture for high-speed RS(255, 251) codec has been corrected =2. The original massage can be recovered by
proposed in [4]. A high-speed architecture for Reed-Solomon employing the RS decoder provided number of errors in the
decoders is proposed in [5]. The complexity of RS encoder received codeword is less than or equal to two.
and decoder increases with the error correcting capability of
the codes. Hence, many researchers have directed their
III. RS ENCODER
efforts to minimize the complexity of RS decoder. In VLSI
system design, power consumption is of prime concern and at In this section a brief overview of RS encoder and its
the same time, the silicon area should be kept as low as corresponding architecture has been discussed. The RS
possible. In this scenario, our aim is to design of a FPGA encoder takes a block of symbols and adds extra parity check
based RS (255, 251) encoder and decoder having two bytes symbols. A RS codeword can be computed from input
error correcting capability. message symbols by employing a generator polynomial. A
In next section, a brief introduction of Reed-Solomon code Generator polynomial depends on the order of the Galois
is given. In section III, RS encoder and its corresponding field over which RS code has been defined and numbers of
architecture has been described. Basic blocks of a RS error to be corrected. The primitive polynomial is decided by
decoder and corresponding architectures have been described the order of the Galois field. One of the primitive polynomial
in section IV. Synthesis result of RS (255, 251) Codec is in GF(28) field is x8+x4+x3+x2+1. Let α be the primitive
presented in Section V and finally the paper is concluded in element in the Galois field in GF(28). Then the generator
Section VI. polynomial for t error correcting RS code is as follows.

Manuscript received on January, 2013.

Anindya Sundar Das, Haldia Institute of Technology, Haldia, India.
Satyajit Das, C R Rao Advanced Institute of Mathematics, Statistics and
Computer Sciences, Hyderabad, India.
Jaydeb Bhaumik, Haldia Institute of Technology, Haldia, India.

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 Design of RS (255, 251) Encoder and Decoder in FPGA

For a double byte error correcting code (t=2), the

corresponding generator polynomial is

Fig3: Block Diagram of Reed-Solomon Decoder

A typical RS decoder has five stages in the decoding cycle,

namely

1. Syndrome Generator
2. Key equation solver -determine error-location
polynomial and error-evaluator polynomial
3. Chien search -solving the error locator polynomial
4. Forney algorithm for calculating the error magnitude
Fig2: Architecture for Reed-Solomon Encoder 5. Error Correction
A. Syndrome Generator
Let the input message polynomial M(x) of the encoder is
Syndrome generation from received codeword is the first
step of decoding process. Here the syndromes are calculated
and it is decided whether there are errors in the received
The corresponding codeword polynomial is given by codeword or not.

This codeword is generated from the input massage

polynomial by using the following formula.

If Q(x) and P(x) are the corresponding quotient and

remainder polynomial when x2tM(x) is divided by the g(x),
then the codeword polynomial can also be expressed in
another way.

Here P(x) is the parity check polynomial. From equation (6)

one can obtained

By adding parity check polynomial P(x) with the x2t M(x)

polynomial, the codeword polynomial C(x) is computed,
Fig4: Architecture for Syndrome Generator
which is completely divisible by g(x).
The syndrome polynomial is generally represented as
IV. RS DECODER
The decoder processes each block and attempts to correct
errors which may occur during transmission or storage. The
decoder divides received codeword polynomial by the RS
code generator polynomial. If the remainder is zero, then no Assume R(x) is the received codeword polynomial
errors are detected, else indicates the presence of errors.

392
 International Journal of Soft Computing and Engineering (IJSCE)
ISSN: 2231-2307, Volume-2, Issue-6, January 2013

Then ith syndrome can be expressed as follows k(r+1) = k(r)+1;

end
(10) end
for i=0 step1 until t-1 do
Where Rn-1 is the first received symbol. step4: ωi(2t) = Si Λ0(2t)+………………+S0 Λi(2t)
output: Λi(2t), i= 0,1…,t ωi(2t), i= 0,….,(t-1)
B. Key Equation Solver
C. Chien-Search Algorithm
The next step, after the computing the syndrome
polynomial is to calculate the error values and their
respective locations. This stage involves the solving of the 2t
syndrome polynomials, formed in the previous stage. These
polynomials have ν unknowns, where ν is the number of
errors occurred in the received codeword. If the unknown
locations are i1, i2... iν , then error polynomial can be
expressed as

where Yr is the magnitude of the rth error at location ir . If xr is

the field element associated with the error location ir, then the
syndrome coefficients are given by
Fig5: Architecture for Chien-Search Algorithm

Where, j = 1,2…2t. Yr is the error value and Xr is the error The Chien-search algorithm is used for evaluating the error
location of the rth error symbol. The error locator polynomial position. The roots of the error locator polynomial are the
can be determined as inverse error locations of the codeword. This algorithm uses
all possible input values and then checks to see if the outputs
are zero. The sum for the odd values (σ1, σ3, σ5……) is
calculated in one side and the sum for the even values (σ0, σ2,
The solution for the coefficients of the σ(x) is representing σ4, σ6,...) is calculated in other . Then the two sums are added.
the error location polynomial. This σ(x) is related with the If the value of the summation is zero in any clock cycle (<n)
error value polynomial by a certain equation, which is known then the position of the clock cycle will determine the error
as the key equation. If the error value is defined by ω(x), the position.
key equation is expressed as
D. Forney Algorithm

Then ω(x) can be used to solve for the error magnitudes

Y1,...... Yv.
These equations are solved in various way. In this paper
we are using „inversion less Berlekamp-Massey algorithm‟
(iBM algorithm). The algorithm is described below:[5]
Initialization
Λ0(0) = b0(0) =1; Λi(0) = bi(0) =0; i = 1,…, t ;
k(0) = 0; γ(0) = 0;
input: Si , i = 0,1,…,2t-1
for r =0 step1 until 2t-1 do
begin
step 1: δ (r) = Sr Λ0(r)+……………..+ Sr-t Λt(r)
Fig6: Architecture for Forney algorithm
step2: Λi(r+1) = γ(r) Λi(r) - δ(r) bi-1(r), (i = 0, 1,…, t )
step3: if δ(r)≠0 and k(r) ≥0 Forney algorithm is used for evaluating the error values.
then The error position and the coefficients of ω(x) is taken here as
begin the input. It is also using Galois field multiplier as the
bi(r+1) = Λi(r) ; Chien-search algorithm. The equation for the error values is
γ(r+1) = δ (r) ; given by:
k(r+1) = -k(r)-1;
end
else
Here indicates the root as computed from the
begin Chien-search and σ′ (x) is the derivative of the error locator
bi(r+1) = bi-1(r); polynomial. The above equation can be written as:
γ(r+1) = γ(r);

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 Design of RS (255, 251) Encoder and Decoder in FPGA

REFERENCES
[1] S. Lin and D. J. Costello, Error Control Coding: Fundamentals and
can be found from the Chien-search Algorithm. Applications. Englewood Cliffs, NJ: Prentice-Hall, 1983.
[2] R. E. Blahut, Theory and Practice of Error Control Codes. Addison-
Wesley, 1983
E. Error Correction [3] S. B. Wicker and V. K. Bhargava, Reed Solomon Codes and Their
Applications, IEEE Press, 1994.
[4] T. K. Matsushima, T. Matsushima, and S. Hirasawa, “Parallel
architecture for high-speed Reed-Solomon codec,” in Proc. IEEE Int.
Telecommunication. Symposium. 1998, pp. 468–473.
[5] D. V. Sarawate and N. R. Shanbhag, “High-speed architectures for
Reed-Solomon decoders,” IEEE Trans. on VLSI Systems, vol. 9, no. 5,
Oct. 2001, pp. 641-655.
[6] E. Mastrovito. “VLSI Architectures for Computations in Galois
Fields,” Ph. D. Dissertation, Dept. of Electrical Engineering,
Linkoping University, Linkoping, Sweden, 1991.
Fig7: Error Correction module [7] L. Song, K. K. Parhi, I. Kuroda. and T. Nishitani. “Hardware/software
codesign of finite field datapath for low-energy Reed-Solomon
codecs,” IEEE Trans. on VLSI Systems, vol. 8. no. 2, Apr. 2000, pp.
Once the error locations and magnitudes are calculated, the 160-172.
error corrector block takes the received code and performs [8] C. Y. Lee, Y. H. Chen, C. W. Chiou and J. M. Lin, “Unified Parallel
Systolic Multipliers over GF(2m),”Journal of Computer Science and
XOR operation with the corresponding error magnitudes, Technology, vol. 22, Jan. 2007, pp. 28-38.
computed at the respective error locations to obtain the
corrected massage symbols.
Mr. Anindya Sundar Das is currently working as a JRF at Haldia
Institute of Technology. He did his M. Tech in Electronics and
Communication Engineering (specialization in Micro Electronics and VLSI
Design) Under West Bengal University of Technology. He has received his
B. Tech degree from Uttar Pradesh Technical University in the year of 2006
Because the error symbols are generated in the reverse
in Electronics and Instrumentation Engineering. His area of research area
order of the received codeword, a FIFO register must be includes Error control coding, Optical Communication and VLSI design.
applied to either the received codeword or the error vector to
match the order of the bytes in both vectors. The output of Mr. Satyajit Das is currently working as a SRF at CR Rao Advanced
Institute of Mathematics, Statistics and Computer Sciences. He did his M.
XOR gate is the decoder's estimated codeword. Tech in Electronics and Communication Engg.(specialization Micro
Electronics and VLSI Design) Under West Bengal University of
V. SYNTHESIS RESULT Technology. He has received his B. Tech degree from West Bengal
University of Technology in the year of 2009 in Electronics and
Every architectural module has been implemented in Communication Engg. His area of research area includes Cryptography and
Verilog and simulated using ModelSim. The design has been VLSI design.
synthesized by Xilinx ISE 7.1i tool. Table I gives the Dr. Jaydeb Bhaumik is currently working as an Associate Professor in
synthesis result of RS (255,251) encoder and decoder. The the Department of Electronics and Communication Engineering, Haldia
target FPGA Device was Spartan3-X3S50TQ144-5. Institute of Technology, Haldia, India. He obtained his PhD degree from G.
S. Sanyal School of Telecommunications, Indian Institute of Technology
Fun. No. of No. No. of No. Max. Min Kharagpur, India in 2010. He received his B. Tech. and M. Tech degrees in
blocks slices of input of freq. Period Radio Physics and Electronics from University of Calcutta in 1999 and 2001
FFs LUTs IOBs (MHz) (ns) respectively. His research interests include Cryptography, Cellular
Automata, Error Correcting Codes, and Digital VLSI Design. He is a
Encoder 46 40 86 67 142.55 7.02
member of IEEE and Cryptology Research Society of India..
Syndrom 56 72 104 50 180.49 5.54
e
calculato
r
Key 662 64 1167 74 102.14 9.80
equation
solver
Chien 60 32 105 66 184.38 5.42
search
block
Forney 292 24 509 90 184.38 5.42
block
Error 28 41 41 50 183.44 5.45
corrector

VI. CONCLUSION
The paper presents a design and implementation of RS
(255, 251) double byte error correcting encoder and decoder
for FPGA platform. Proposed Reed-Solomon codec has been
synthesized by employing Xilinx ISE 7.1i tool. The result
shows that it is very effective as it works faster and requires
less hardware.

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