Chapter 4: Advance microprocessor

In the non-contiguous memory allocation technique, different parts of the same process are
stored in different places of the main memory. Types:

1. Paging
2. Segmentation

Paging
Paging is a non-contiguous memory allocation technique in which secondary memory and
the main memory is divided into equal size partitions. The partitions of the secondary
memory are called pages while the partitions of the main memory are called frames . They
are divided into equal size partitions to have maximum utilization of the main memory and
avoid external fragmentation.

Example: We have a process P having process size as 4B, page size as 1B. Therefore there
will we four pages(say, P0, P1, P2, P3) each of size 1B. Also, when this process goes into
the main memory for execution then depending upon the availability, it may be stored in non-
contiguous fashion in the main memory frame as shown below:

Translation of logical Address into physical Address

As a CPU always generates a logical address and we need a physical address for accessing
the main memory. This mapping is done by the MMU(memory management Unit) with the
help of the page table . Lets first understand some of the basic terms then we will see how
this translation is done.

• Logical Address: The logical address consists of two parts page number and page
offset.
1. Page Number: It tells the exact page of the process which the CPU wants to access.

2. Page Offset: It tells the exact word on that page which the CPU wants to read.

Logical Address = Page Number + Page Offset

• Physical Address: The physical address consists of two parts frame

number and page offset.
1. Frame Number: It tells the exact frame where the page is stored in physical memory.

2. Page Offset: It tells the exact word on that page which the CPU wants to read. It requires
no translation as the page size is the same as the frame size so the place of the word which
CPU wants access will not change.

Physical Address = Frame Number + Page Offset

• Page table: A page stable contains the frame number corresponding to the page
number of some specific process. So, each process will have its own page table. A
register called Page Table Base Register(PTBR) which holds the base value of the
page table.

Advantages of Paging

1. There is no external fragmentation as it allows us to store the data in a non-contiguous

way.
2. Swapping is easy between equal-sized pages and frames.

Disadvantages of Paging

1. As the size of the frame is fixed, so it may suffer from internal fragmentation. It may
happen that the process is too small and it may not acquire the entire frame size.
2. The access time increases because of paging as the main memory has to be now
accessed two times. First, we need to access the page table which is also stored in the
main memory and second, combine the frame number with the page offset and then
get the physical address of the page which is again stored in the main memory.
3. For every process, we have an independent page table and maintaining the page table
is extra overhead.
Segmentation
In paging, we were blindly diving the process into pages of fixed sizes but in segmentation,
we divide the process into modules for better visualization of the process. Here each segment
or module consists of the same type of functions. For example, the main function is included
in one segment, library function is kept in other segments, and so on. As the size of segments
may vary, so memory is divided into variable size parts.

Translation of logical Address into physical Address

As a CPU always generates a logical address and we need a physical address for accessing
the main memory. This mapping is done by the MMU(memory management Unit) with the
help of the segment table .

Lets first understand some of the basic terms then we will see how this translation is done.

• Logical Address: The logical address consists of two parts segment

number and page offset.
1. Segment Number: It tells the specific segment of the process from which the CPU wants
to read the data.

2. Segment Offset: It tells the exact word in that segment which the CPU wants to read.

Logical Address = Segment Number + Segment Offset

• Physical Address: The physical address is obtained by adding the base address of
the segment to the segment offset.
• Segment table: A segment table stores the base address of each segment in the main
memory. It has two parts i.e. Base and Limit . Here, base indicates the base address
or starting address of the segment in the main memory. Limit tells the size of that
segment. A register called Segment Table Base Register(STBR) which holds the base
value of the segment table. The segment table is also stored in the main memory itself.

Advantages of Segmentation

1. The size of the segment table is less compared to the size of the page table.
2. There is no internal fragmentation.

Disadvantages of Segmentation

1. When the processes are loaded and removed ( during swapping ) from the main
memory then free memory spaces are broken into smaller pieces and this causes
external fragmentation.
 2. Here also the time to access the data increases as due to segmentation the main
memory has to be now accessed two times. First, we need to access the segment table
which is also stored in the main memory and second, combine the base address of the
segment with the segment offset and then get the physical address which is again
stored in the main memory.

Paging Segmentation

In paging, the program is divided into In segmentation, the program is divided into
fixed or mounted size pages. variable size segments.

For the paging operating system is

For segmentation compiler is accountable.
accountable.

Page size is determined by hardware. Here, the segment size is given by the user.

It is faster in comparison to
Segmentation is slow.
segmentation.

Paging could result in internal Segmentation could result in external

fragmentation. fragmentation.

In paging, the logical address is split Here, the logical address is split into segment
into a page number and page offset. number and segment offset.

While segmentation also comprises the

Paging comprises a page table that
segment table which encloses segment
encloses the base address of every page.
number and segment offset.

The page table is employed to keep up

the page data.

In paging, the operating system must In segmentation, the operating system

maintain a free frame list. maintains a list of holes in the main memory.

Paging is invisible to the user. Segmentation is visible to the user.

In paging, the processor needs the page In segmentation, the processor uses segment
number, and offset to calculate the number, and offset to calculate the full
absolute address. address.

It is hard to allow sharing of procedures Facilitates sharing of procedures between the

between processes. processes.
 Pipeline structure:

A pipeline in a microprocessor is a technique that allows multiple instructions to be executed

in parallel by breaking down a sequential process into sub-operations. This is achieved by
storing and prioritizing instructions, and then allowing the processor to perform each
instruction in multiple steps.

Instruction Pipeline In this a stream of instructions can be executed by overlapping fetch,

decode and execute phases of an instruction cycle. This type of technique is used to increase
the throughput of the computer system. An instruction pipeline reads instruction from the
memory while previous instructions are being executed in other segments of the pipeline. Thus
we can execute multiple instructions simultaneously. The pipeline will be more efficient if the
instruction cycle is divided into segments of equal duration.

Feature of 8086 microprocessor:

It is a 16-bit μp.
8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
• It can support up to 64K I/O ports.
• It provides 14, 16 -bit registers.
• Word size is 16 bits and double word size is 4 bytes.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal timing.
• 8086 is designed to operate in two
8086 is designed to operate in two modes, Minimum and Maximum.
• It can prefetches up to 6 instruction bytes from memory and queues them in order to speed
up instruction execution.
• It requires +5V power supply.
• A 40 pin dual in line package.
• Address ranges from 00000H to FFFFFH
• Memory is byte addressable - Every byte has a separate address.

Feature of 80286 microprocessor:

Protected mode: The 80286 was the first 8086 CPU to support protected virtual-address mode,
which allowed for multitasking and memory protection.

• Virtual memory: The 80286 supported virtual memory, which allowed programs to use more
memory than was physically available.
• Instruction set: The 80286 had an improved instruction set with new addressing modes and
instructions.
• Architecture: The 80286 had a 16-bit architecture and a 24-bit address bus, which allowed it to
access up to 16 MB of memory.
• Clock speed: The 80286 had a clock speed range of 6 to 25 MHz.
• Functional parts: The 80286 had four functional parts: the address unit, the bus unit, the
instruction unit, and the execution unit.
• Co-processor: The 80286 had a co-processor.
• Predecessor: The 80286 was the successor to the 8086 and 80186 processors.

Features of 80386

• As it is a 32-bit microprocessor. Thus has a 32-bit ALU.

• 80386 has a data bus of 32-bit.
• It holds an address bus of 32 bit.
• It supports physical memory addressability of 4 GB and virtual memory addressability of
64 TB.
• 80386 supports a variety of operating clock frequencies, which are 16 MHz, 20 MHz, 25
MHz, and 33 MHz.
• It offers 3 stage pipeline: fetch, decode and execute. As it supports simultaneous fetching,
decoding, and execution inside the system.
Modes: protected mode, virtual mode
Basically, it has 6 functional units which are as follows:

1. Bus Interface Unit

2. Code Fetch Unit
3. Instruction Decode Unit
4. Execution Unit
5. Memory Management Unit

• Microarchitecture: The Pentium 4 uses the NetBurst microarchitecture, which has four main
sections: the front end, execution engine, integer and floating-point units, and memory
subsystem.
• Clock speed: The Pentium 4 was originally released with a clock rate of 1.4–1.5 GHz, but later
models could reach speeds of up to 3.8 GHz.
• Memory: Pentium 4 motherboards can use RDRAM, SDRAM, DDR SDRAM, or DDR2
SDRAM, but most use DDR or DDR2 SDRAM.
• SSE2: The Pentium 4 Willamette introduced SSE2, which improved performance for
multimedia, content creation, and scientific and engineering applications.
• SSE3: The Pentium 4 Prescott introduced SSE3 and later 64-bit technology.
• Hyper-Threading Technology (HTT): Later versions of the Pentium 4 introduced Hyper-
Threading Technology.
• Power consumption: The Pentium 4 consumes 55 watts of power at 1.5 GHz.
• System bus: The Pentium 4 has a 3.2 GB/second system bus.

Comparison:

Specifications 80286 80386 80486

CPU Speed 6 to 25 MHz 12 to 40 MHz 16 to 100 MHz

Cores 1 1 1

RAM 16MB 4GB 4GB

Functional Units 4 6 9

Pipeline stages 3 3 5

Cache off chip 0 YES (Support) YES (Support)

Cache on chip 0 0 8 KB

Transistors 134,000 275,000 >1000000

Parameter 8086 80386 Pentium

Year of 1978 1985 `1993

Introduction

Data Bus 16 bit 32 bit 128 bit

`Address 20 bit 32 bit 64 bit

Bus
Parameter 8086 80386 Pentium

Physical 1 MB 4 GB 4 GB
memory

Register 16 bit 32 bit 32 bit

size

Voltage 5V 5V 3.3V
required

Clock type 1x 2x 3x

Pipelining Yes Yes Yes

Operating 1.,Maximum 1.,Real 1.,Protected

modes mode2. mode,2.,Protected mode,2.
Minimum mode,Virtual Real-
mode mode Address
mode