Question 1.
Wafers
(a) Describe one method for generating a silicon-on-insulator (SOI) wafer.
(4 marks)
(b) Give one disadvantage of using SOI wafers.
(2 marks)
(c) Name two main epitaxial growth techniques for semiconductors.
(4 marks)
(d) Name an epitaxial growth technique for semiconductors that can also be used for
depositing non-semiconducting films?
(1 mark)
(e) Explain why the growth rate of epitaxial silicon is less dependent on temperature at
higher growth temperatures than lower growth temperatures.
(3 marks)
(f) Will auto-doping increase or decrease at higher temperature?
(1 mark)
Question 2. Dielectrics
(a) Name two widely used dielectrics in semiconductor processing.
(4 marks)
(b) Suggest a deposition technique for each of the dielectrics in part (a).
(2 marks)
(c) Explain why thermal oxidation can’t be used for interlayer dielectrics (ILD) in the
back-end-of-line.
(3 marks)
(d) Is the thermal oxidation rate faster for wet oxides or for dry oxides?
(1 mark)
(e) Explain how atomic layer deposition (ALD) achieves well-controlled thickness.
(3 marks)
(f) Name one device region where ALD is useful.
(2 marks)
Question 3. Lithography
(a) What is meant by the resolution of a lithography system?
(3 marks)
(b) In advanced electronic devices, does resolution need to be smaller or larger?
(2 marks)
(c) Why is resolution better using electron beams than UV light?
(2 marks)
(d) After exposure, does positive resist become more soluble or less soluble in
developer solution?
(2 marks)
(e) Draw a cross-sectional schematic diagram showing a positive resist pattern after
developing. Include the mask pattern.
(4 marks)
(f) What is notable about the masks in extreme ultra violet (EUV) lithography?
(2 marks)
Question 4. Etch
Three techniques used to etch (remove) unwanted materials in device fabrication are: (i)
wet etch; (ii) dry etch (iii) chemical mechanical polishing (CMP).
(a) Which etch technique can etch selectively along crystallographic planes?
(2 marks)
(b) Which technique uses a slurry with particles to remove material?
(2 marks)
(c) Which technique uses a plasma to remove material?
(2 marks)
(d) Which technique has an etch profile that depends on gas pressure?
(2 marks)
(e) Which technique etches both sides of the wafer?
(2 marks)
(f) Which technique may lead to scratches?
(2 marks)
(g) Why does copper interconnect use CMP to remove excess material?
(3 marks)
Question 5. Wafer defects
(a) What are the two main elements in silica (silica is the raw substance from which
most semiconductor wafers are made)?
(2 marks)
(b) Explain the purification process of silica.
(3 marks)
(c) Give an example of useful impurities in semiconductor materials.
(2 marks)
(d) Explain how the useful impurities in part (c) improve device performance.
(2 marks)
(e) Give an example of defects in semiconductors.
(2 marks)
(f) Explain how the defects in part (e) degrade device performance.
(2 marks)
(g) Name a piece of characterisation equipment that can be used to study
semiconductor defects?
(2 marks)
Question 6. Characterisation
(a) What is secondary ion mass spectroscopy (SIMS) used to measure?
(2 marks)
(b) Is SIMS an electrical or physical characterisation technique?
(1 mark)
(c) Sketch an output from a SIMS measurement through an implanted source/drain
region of a metal-oxide-semiconductor field-effect transistor (MOSFET).
(6 marks)
(d) Show on the sketch changes that occur after a high temperature anneal.
(4 marks)
(e) Name an implant that could be used for the source/drain region of a silicon n-type
MOSFET?
(2 marks)
