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Logic Design Lab Report (24F-CS-000)

The document outlines the implementation of a 16x1 multiplexer and various flip-flops (D, S-R, J-K) with their truth tables and circuit diagrams. It also includes the design of different counters, such as a 2-bit synchronous counter and an asynchronous decade counter, along with their respective truth tables. Additionally, there are sections on binary to Gray code conversions.

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JUNAID JEE
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9 views12 pages

Logic Design Lab Report (24F-CS-000)

The document outlines the implementation of a 16x1 multiplexer and various flip-flops (D, S-R, J-K) with their truth tables and circuit diagrams. It also includes the design of different counters, such as a 2-bit synchronous counter and an asynchronous decade counter, along with their respective truth tables. Additionally, there are sections on binary to Gray code conversions.

Uploaded by

JUNAID JEE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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S0Implementation of a 16x1 MULTIPLEXER

III)

Truth Table:

Input I S0 S1 S2 S4 Y output

I0 = 1 0 0 0 0 1

I1 = 1 0 0 0 1 1

I2 = 1 0 0 1 0 1

I3 = 1 0 0 1 1 1

I4 = 1 0 1 0 0 1

I5 = 1 0 1 0 1 1

I6 = 1 0 1 1 0 1

I7 = 1 0 1 1 1 1

I8 = 1 1 0 0 0 1

I9 = 1 1 0 0 1 1

I10 = 1 1 0 1 0 1

I11 = 1 1 0 1 1 1

I12 = 1 1 1 0 0 1

I13 = 1 1 1 0 1 1

I14 = 1 1 1 1 0 1

I15 = 1 1 1 1 1 1

Circuit Diagram:
Experiment 8
Implementation of Flip flops, D, S-R, J-K.
D Flip-Flop:

Truth Table:

D Q Description

0 0 Stores 0

1 1 Stores 1

Diagram:

S-R Flip Flop:

Truth Table:

S R Q Description

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Invalid Invalid
condition
Diagram:

J-K Flip Flop:

Truth Table:

J K Q Description

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 ¬Q Toggle (Q
flips)

Diagram:
Experiment 9
Implementation of Counters

1) 2-bit Synchronous Counter:

Diagram:

2) Asynchronous Decade Counter:

Decimal Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

0 (reset) 0 0 0 0
Diagram:

3) 3-bit Asynchronous Counter:

Diagram:
Open Ended LAB 1

Experession:
a)

b)
a)

b)
Binary Gray

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

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