Educational Strategy The program leverages IISc's century-long legacy of academic excellence and its status as an Institute of Eminence to deliver a cutting-edge curriculum that includes: Hands-On Learning: Utilizing state-of-the-art computational tools like TCAD (Technology Computer-Aided Design) and advanced compute clusters, the program offers practical experience in semiconductor design and process simulation. * Industry-Relevant Skills: Courses are designed to cover the entire spectrum of semiconductor manufacturing, from basic concepts to complex device fabrication techniques, ensuring that students gain both breadth and depth of knowledge. * Real-World Application: By integrating theoretical knowledge with real-world applications, the program prepares students to tackle industry challenges immediately upon graduation.Inspiration and Engagement To truly fascinate students, the ISWDP employs innovative teaching methodologies that make complex concepts accessible and engaging: e Interactive Sessions: Led by experts, these sessions delve into the complexities of semiconductor processes, encouraging students to question, explore, and understand the intricacies of the field. Problem-Solving Workshops: Students face real-life scenarios that require them to apply their knowledge, fostering critical thinking and problem-solving skills. Industry Exposure: Through partnerships with leading tech companies, students gain insights into the semiconductor industry, experiencing first-hand the challenges and rewards of the field.Billions of transistors, 10 nm process, 2021 Point contact transistor} | Fully Transistorized (@Bell Labs, 1947_||_ Computer, TRADIC, 1954 _ First Silicon transistor, Tanenbaum at Bell Labs, 1954 Invention of the MOSFET transistor (Atalla and Kahng at Bell Labs), 1959 First microprocessor (Intel "y 4004, 2300 transistors, 10,000nm size), 1974More than Moore: Functionality extension Giant P's ™ t Photonie Integration Log (Transistor density) Hybrid integration of Jemicond 2005 «200 =—=«2015 «2020 «2025 «20302085 Year Reducing form factor, increasing functionality Qincreased design complexity, increased necessity ofWhat Keeps the Semiconductor Development Rolling? >Cutting edge research »New device structures > paradigm shift from planar to 3D structures, finFETs, HEMTs »New material integrations, like strained Si:Ge for enhanced mobility, shifting to wide band gap semiconductors like GaN, SiC, Ga203, Diamond Moving to 2D and even single atom devices !! > Reliability improvement through innovation !! > Improved understanding of physical mechanisms >Bringing down cost of research, development and production. Time toUnderstanding Device Design : Just Silicon >Control Conductivity qnu + 1 = Np (Considering complete ionization) »Increasing Np should then increase conductivity! Wait!! > it reduces mobility ! = Hp Ho = Umin + {_——-—a wo 14 (No oF 0 07a! Nres Impurity concentration (em~%) » Should consider trade-off Mobility (em?/V-s) Non-uniform Incomplete _ionizatio1A Step Ahead: Designing of a Diode Depletion Region et eV _ [eDpPno , @Datpo saufn(§) af nef + What happens if we increase py and nyo? AT Reeries + but ub D =p. b> Ist Epeax T 24 NaNp 1/2 lEpeak = 2 . Yu -v0| + Performance trade-off and impact on reliability * Reduce pro and nyo ? > Rseries TDesign seems complex ? Wait !! this was ideal diode + Recombination current at lower forward biases !! cenw __(#@(#)-) Irae = poe 29 Voi—Va Vtnte A (1+ KT]q "2°" 1. Free E(-Er To = 7 (te kT +tpe kT ) * More trade-offs involved !! + Imagine computing for a modern day device which involves hetero-junctions!!Should we increase complexity? > Planar MOSFET Vota = Ves Vr fies Mat Vos.> Vast vo n-channel enhancement mode MOSFET wn fen Wena Io inear = A822 (2(Ves ~ Ve Vos ~ VB, losat, = "286 Vas — Vr}? iia, can | eke in = ay [Qo max)| = eNexers tar = (SL2]”, bp = Veln(%2) dns = n= (x! +=)Designing Planar MOSFET What happens if we increase N,? eee + Affects Qsp > can tune V;, Body effect? AV = 2a = — 26¢y + Vs8 — en + Increase electric field near drain > feet early failure and reliability concerns ana | ane f+ Reducing N, + Reduced field near drain edge > Great !! + Increased voltage drop in substrate > false triggering of the parasitic BUT > failure + Punch-through!! > more prominent in short channel devices !! + Trade-off between reliability and performance !! oC + More complex analysis in modern day devices > How to design?Designing Planar MOSFET f= Im WCoxVsat_ _ Ysat Cut-off frequency: fr = 2nCq 2m(CoxWL) 2k Let us try to improve f > L will have to be reduced ary Hen (He) ’ Ww Vas = 0.125Should we try and increase complexity further? » Non-planar structures? FinFETs!! + The potential distribution, electric fields, and carrier densities will have to be analyzed in 3- dimensions! Erica} * Correlated design = parameters = > —/mportant to remember > Time Simultaneous optimization > exponentially iend coat to cevelgnment arelenseal: increasing design time >» What happens when we integrate different materials? Different band gap, different mobility, formation of quantum wells !! > Very critical process control > How do we estimate?Is Understanding Device Design Enough? > Process challenges in fabricating modern-day devices > The process limitation induced impact on device design > The device design has to take into account the exact device structure!! fenwe30 . (a) (b) Chi, Min-hwa. “Challenges in Manufacturing FinFET at 20 nm node and beyond.” (2012).Is Understanding Device Design Enough? lon implantation: the trade-off between doping control, cost and crystal damage lon implantation on Si with Ga* ionsTypical Semiconductor Device Development Cycle (Areal ] (Speedt] { PowerDensity- } (Cost! } [Time to Develop! Design Requirement Performance and ReliabiliTCAD Based Approach: Addressing these Challenges Structure Editor: First hand generation of any novel structure. Simulation time: a few minutes. Quick conceptualization and testing. Zz xy Doping fom) 12020 12e7 12est4 1.90612 2.00415 2.00+18TCAD Based Approach: Addressing these Challenges Fab Process simulator: Effectively simulates different fabrication process steps including etching, ion implantation induced doping profile, damage, the impact of annealing temperature on dopant diffusion, and stress profiles,.... SimulatiorTCAD Based Approach: Addressing these Challenges Device simulator: DC, AC, Transient performance and reliability analysis, device-circuit co-simulation. Physical insights.oe TCAD is a vehicle to design, develop, and understand semiconductor fab processes and design better. AVERY ery om m=y.dc-1a 1S NVZ-) are Looe] vehicle to learn semiconductors better. Let’s understand this most sophisticated industry standard tool in some detail.TCAD — Technology Computer Aided Design Device Simulation pole —_— Structure Trench Cridton 3D Doping Pie Focus: The stuctre, doping, sresses, meshing SE spursys: Focus: Electrica thermal, optical charactrisiesWhat is Process Simulation? * Virtual representation or simulation of the manufacturing process of semiconductor chips. ~ Focused on the smailest building blocks: the individual transistor and their immediate environment + Sentaurus Process: ~ Focused on doping implant and difusion, and oxidation. ~ ... more phenomenological on etching and deposition. + Doping: + etching: Leary changing the electra properies Removing mater wih eter reactive of the semiconductor ‘ons rscivets, + Implanting: + Deposition “ Shooting’ ons ito the semiconcuctor ‘Growing material typical rom compounds + Difusion/Annealing: inthe gas envionment Heat treatment to tive the fons in deeper, + Masking: ‘activate them, and to heal damage. Using the layout ike 2 masking tape to F ‘expose or protect certain area 'emiconducto ino an insulator. . enProcess Flow Descriptions Are Input to Process Simulation 28nm Bulk CMOS a Key Process Techniques: Isolation fl Gate stack dep (dummy gate) Lithography Gate patteming Halos / extensions Implantation SID silicidation A CESL + ILDO dep / CMP re Diffusion, Annealing Dummy poly-Si gate removal Dummy dielectric removal Spacers + S/D + RTA High-x, MG dep Thermal Oxidation 1LD1 deposition ‘Contact formation BEOL Etching and Deposition Snlon Implantation + Ion implantation into on-axis crystals leads to many ions experiencing small angle scattering and channeling deep into the crystal + Their stopping is then dominated by electronic drag only, which results in a channeling “tail” + The resultant profile is described by a “dual- Pearson’ distribution + Tilting the wafer reduces channeling + Implantation through a thin (screen) oxide also reduces channelingDiffusion Dittusing is modelled either modelled atomistic or in a continuum with a set of partial differential equations (PDE) In the Frank-Tumbull mechanism, interstitial dopants or In fe Kok: out spechianismisestexwersttials Kid opant-intersttal pairs occupy vacant sites and become out substitutional dopants, substitutional dopants. _ econSentaurus Process Simulator + General purpose multcimenscnal(20/2D) process simulator + tntegrated 30 geometric modetng engine + API Tor user-defined models + Advanced physical models: = Anal and Were Caro mpanston Doping Atoms nanowire Mechanical Stress Trench OxidationWhat does Sentaurus Process “look” like? *) Batch tool with Tol-based input language (... python version in the works!) Typical simulation tun times: 2d: several min to several hours. 3d; several hours to several days a 5 al 8 4 | 2 *Sentaurus Structure Editor + Geometrical operations + Easy to use GUI + Scripting language + Advanced geometrical modeling with analytic doping definitions, + Direct interface to meshing engines is pixels with micro lenses Sentaurus Structure Editor GUIProcess Explorer + From layout files and process step description Process Explorer builds high-fidelity topographical 3D models allowing DOE creation based on a collaborative database + Key capabilities: = — GUI and batch support ~ Support for large layouts = Fast tum around time + Advantages: ~ Collaborative Environment ~ Different technologies = Value Links with TCAD =3 oo Patan EE aWhat is Sentaurus Mesh?What is Device Simulation? + Virtual tests of the electrical and thermal behavior of the transistors ~ Focused on the smallest building blocks: the individual transistor and their immediate environment. = Solving Drift-Diffusion Transport equations: Poisson + Carrier Continuity Ea, = Can also solve the Heat Transport equationWhat does Sentaurus Device “look” like? Batch tool (basic Tel or Python layers available for scripting) Typical simulation run times: 2d: several min to several hours. 3d: several hours to several daysSentaurus Workbench + TCAD framework environment + Project management + Design-of-experiments, and optimization + Job farming :Sentaurus Visual: TCAD Data Visualizer + Enhanced GUI experience = 2/30 fields = XY data A — S:parameter plots — Overlay and difference plots + Powerful scripting capabilities = Python and TOL Who uses it? br + Everyone who uses TCAD * _ STCSynopsys TCAD Product Family So Visual atesAdvanced Logic: Nanosheet Transistors ‘Alternative Interconnect Metals eel sy / Dopant Diffusion / ‘Activation in SID —IGBT Chip to Package and System Simulation using TCAD Tools (DCDC Converter System) ‘eaten