Advanced
Physical Design
Turn Circuits into Silicon –
Become a Physical Design Engineer
Offline/Online Mode
+91 8309818310 www.chipxpert.in
Hyderabad, Bengaluru
About us
Trainers Details
ChipXpert VLSI Training
Institute is a premier institution dedicated to 15+ years of industry experience in VLSI Physical
providing state-of-the-art training in Very- Design, working with global semiconductor
leaders like NVIDIA, Qualcomm, Intel, and AMD.
Large-Scale Integration (VLSI) design and
Deep expertise in RTL to GDSII flow, including
semiconductor technology. With our
Floorplanning, Power Planning, Placement, CTS,
commitment to bridging the gap between Routing, and Physical Verification.
academic knowledge and industry Hands-on experience in advanced technology
requirements, we ensure aspiring engineers nodes (7nm, 5nm, 3nm) with successful tape-
are fully prepared for successful careers in the out of multiple complex SoCs.
fast-paced semiconductor and electronics Proficient in Static Timing Analysis (STA), Signal
industry. Our programs are designed by Integrity, Clock Tree Optimization, and Timing
industry veterans, integrating theoretical Closure techniques.
Strong background in Low Power Design
foundations with practical expertise.
methodologies using UPF/CPF, and handling
ECOs in late-stage design.
Eligibility Criteria Extensive tool knowledge in Cadence,
Synopsys, and Mentor Graphics EDA tools,
B.Tech/B.E final-year students
aligned with current industry practices.
(ECE/EEE/Instrumentation). Proven track record of mentoring and training
M.Tech/M.Sc 1st/2nd-year students freshers and professionals with a focus on
(VLSI/Embeded). real-time, hands-on learning.
Graduates with completed B.Tech/M.Tech degrees. Training programs are designed to bridge the
gap between academia and industry, making
Modes of Training Offered students job-ready for VLSI roles.
Classroom-Based Offline Training
Interactive Online Training Sessions
Industry-Focused Internship Program
Physical Design Course Overview
Unique Features
ChipXpert proudly introduces its
Guaranteed 100% Placement Assistance
Advanced Physical Design (PD) Course,
Impressive Hands-On 24/7 Labs & Projects
specially designed for students and
Curriculum with Latest Industry Tools
professionals aiming to build a strong career in
Corporate-Level Professional Training
VLSI backend design. This course is curated by
Flexible Training Modes with 24/7 eLearn Access
industry experts with over 15 years of experience
Expert Trainers and Guest Sessions
at leading semiconductor companies like
NVIDIA, Qualcomm, Intel, and AMD. It offers in-
Learning Outcome depth training on the complete RTL to GDSII
flow, covering advanced topics such as
Understand RTL to GDSII flow and design stages. Floorplanning, Power Planning, Placement,
Perform Floorplanning, Power Planning, and Placement. Clock Tree Synthesis (CTS), Routing, Static
Implement Clock Tree Synthesis (CTS) and Routing. Timing Analysis (STA), Low Power Design using
Analyze and fix timing violations using STA. UPF/CPF, Physical Verification (DRC/LVS), and
Apply Low Power Design techniques (UPF/CPF). Tape-out preparation. Learners will also gain
Run DRC/LVS checks and understand Physical Phone Number
hands-on experience in TCL scripting for design
Verification.
Handle ECOs and prepare for Tape-out.
+123-456-7890
automation, and real-time exposure to
industry-standard EDA tools and interview
Gain experience with industry-standard EDA tools. preparation, We equips learners with job-ready
Learn and apply TCL scripting for tool automation skills to succeed in top VLSI companies.
COURSE CURRICULUM
S.No Module Topic Module Description
CMOS fundamentals, digital logic basics, combinational and sequential
Basics of CMOS and Digital
1 circuits, timing concepts, and standard cells in the context of physical
Electronics
implementation.
UNIX commands, file systems, shell scripting for automating flows, and data
2 Introduction to UNIX & Scripting
management in Physical Design (PD) environments.
Verilog RTL and Synthesis Verilog RTL structure, synthesis flow, constraints (SDC), timing exceptions,
3
Fundamentals netlist generation, and quality checks pre-physical design.
DFT basics, scan insertion, MBIST, LBIST, boundary scan, ATPG, and
4 Design for Test (DFT) Fundamentals
integrating DFT requirements with physical design flows.
Floorplan strategies, die/core planning, aspect ratio, IO placement, macro
5 Floorplanning and Power Planning placement, power grid planning, and budgeting for congestion and routing
resources.
Placement strategies for standard cells, legalizing placement, optimizing for
6 Placement Flow
timing and congestion, and floorplan-aware placement methodologies.
CTS fundamentals, clock tree structures (H-tree, Fishbone), insertion delay,
7 Clock Tree Synthesis (CTS) skew management, buffer/inverter selection, and CTS timing closure
techniques.
Global and detail routing, track assignment, DRC-clean routing, antenna
8 Routing and Optimization effects, shielding, congestion resolution, and post-route optimization for
timing and SI.
Timing concepts, setup/hold violations, slack analysis, timing reports, ECO
9 Static Timing Analysis (STA)
for timing fixes, and timing closure using PrimeTime/Tempus tools.
Introduction to PV tools (Calibre, ICV), running DRC, LVS, ERC checks,
10 Physical Verification (DRC, LVS, ERC)
debugging violations, and preparing layouts for signoff tapeout.
Crosstalk, coupling noise, IR drop, EM violations, mitigation strategies, SI-
11 Signal Integrity and IR Drop Analysis
aware routing, and analysis flows for deep-submicron technologies.
Metal fill insertion, antenna violation fixes, ECO flows (functional and
12 Antenna Fixes and ECO Flow
timing), and signoff ECO closure processes for final GDS preparation.
Low Power Design and Multi-Voltage UPF/CPF methodologies, power domains, level shifters, isolation cells,
13
Domains retention cells, and power-aware physical design and verification practices.
Final signoff processes including LVS, DRC, timing, SI, IR drop closure,
14 Tapeout and Signoff Closure preparing GDSII for tapeout, and checklists for delivering production-quality
designs.
Hands-on with tools like Innovus, ICC2, PrimeTime, Tempus, Calibre, ICV,
Industry-Standard PD Tools and
15 DFTMAX, and Redhawk. Understanding tool-specific best practices and
Flows
integration flows.
End-to-end block-level project: Synthesis to GDSII, including timing closure,
16 Project & Final Evaluation DFT integration, PV signoff, IR/EM analysis, and final evaluation through
industry-standard reviews.
Placement Process
SOFT SKILLS
PLACEMENT REGISTRATION TRAINING
MOCK INTERVIEWS WITH
INDUSTRY EXPERTS
MOCK INTERVIEW
SESSIONS
RESUME BUILDING
PLACEMENT DRIVES &
INTERVIEWS
REAL-TME INDUSTRIAL
INDUSTRY CONNECT & GUEST ENGINEERS PROJECT
CAREER GUIDANCE
SELECTED ?
COURSE COMPLETION
CERTIFICATE
JOB ONBORADING PROCESS
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