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Verilog Assignment1 KVLSI2501128

The document outlines assignments for system design using Verilog, including a Mealy-based sequence detector, a washing machine FSM, and an I2C bus protocol. Each section provides design code and test bench examples for the respective systems. The document is structured with specifications, state diagrams, and detailed Verilog implementations.

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karan2004sss
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16 views13 pages

Verilog Assignment1 KVLSI2501128

The document outlines assignments for system design using Verilog, including a Mealy-based sequence detector, a washing machine FSM, and an I2C bus protocol. Each section provides design code and test bench examples for the respective systems. The document is structured with specifications, state diagrams, and detailed Verilog implementations.

Uploaded by

karan2004sss
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 13

SYSTEM DESIGN USING VERILOG ASSIGNMENT 7/6/2025

Question 1: Design a single State Transition Diagram (STD) for a Mealy-based


sequence detector that detects overlapping occurrences of the following binary
sequences: a) 01011 b) 11001 c) 1100 Write down the Verilog code for the generated
STD for the given sequences

Design Code Test bench


module mealy_seq_dec(input X,clk,rst,output module test_mealy;
reg Y); wire Y;
reg [3:0] ps,ns; reg X, clk, rst;
parameter idle = 4'b0000; mealy_seq_dec dut(X,clk,rst,Y);
parameter s0 = 4'b0001;
parameter s01 = 4'b0010; initial begin
parameter s010 = 4'b0011;
parameter s0101 = 4'b0100; clk =0 ;
parameter s1 = 4'b0101; rst = 0;
parameter s11 = 4'b0110; #13 rst = 1;
parameter s110 = 4'b0111; #10 X= 0;
parameter s1100 = 4'b1000; #10 X= 1;
always @ (posedge clk ) begin #10 X= 0;
if(!rst) begin #10 X= 1;
Y <=0; #10 X= 1;
ps <= 0; #10 X= 0;
end #10 X= 0;
else #10 X= 1;
ps<= ns; #200 $finish;
end end
always @(X,ps) begin always #5 clk = ~clk;
case (ps)
idle : begin Y=0; if (X) ns = s1; else ns = s0; end endmodule
s0 : begin Y=0; if (X) ns = s01; else ns = s0; end
s01 : begin Y=0; if (X) ns = s11; else ns = s010;
end
s010 : begin Y=0; if (X) ns = s0101; else ns =
s0; end
s0101 : if (X)begin Y = 1; ns = s11; end else
begin Y = 0; ns = s010;end
s1 : begin Y=0; if (X) ns = s11; else ns = s0; end
s11 : begin Y=0; if (X) ns = s11; else ns = s110;
end
s110 : if (X) begin Y=0; ns = s01; end else
begin Y = 1; ns = s1100; end
s1100 : if (X)begin Y = 1; ns = s01; end else
begin Y = 0; ns = s0;end
default : begin Y = 0; ns = idle; end
endcase

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SYSTEM DESIGN USING VERILOG ASSIGNMENT 7/6/2025

end
endmodule

OUTPUT

State Diagram

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Question 2: Design a Verilog module for a Washing Machine with the following
specifications: Functional Requirements: The machine has six states: a) IDLE:
Waiting for user to start b) FILL: Filling water (2 minutes) c) WASH: Washing
clothes (20 minutes) d) RINSE: Clothes Rinse (10 minutes) e) DRAIN: Draining
water (3 minutes) f) SPIN: Spin clothes (5 minutes) After completing all these steps,
a DONE/BEEP signal should be high for 30 seconds.

Design Code Test bench


module WashingMachineFSM (
input clk, `timescale 1ns / 1ps
input reset,
input start, module tb_WashingMachineFSM;
output reg [2:0] state,
output reg beep reg clk;
); reg reset;
typedef enum logic [2:0] { reg start;
IDLE = 3'b000, wire [2:0] state;
FILL = 3'b001, wire beep;
WASH = 3'b010,
RINSE = 3'b011, WashingMachineFSM uut (
DRAIN = 3'b100, .clk(clk),
SPIN = 3'b101, .reset(reset),
DONE = 3'b110 .start(start),
} state_t; .state(state),
state_t current_state, next_state; .beep(beep)
reg [11:0] counter; );
localparam FILL_TIME = 120;
localparam WASH_TIME = 1200; always #5 clk = ~clk;
localparam RINSE_TIME = 600;
localparam DRAIN_TIME = 180; initial begin
localparam SPIN_TIME = 300; $display("Time\tState\tBeep");
localparam DONE_TIME = 30; $monitor("%0t\t%0d\t%b", $time, state,
beep);
always @(posedge clk or posedge reset)
begin clk = 0;
if (reset) begin reset = 1;
current_state <= IDLE; start = 0;
counter <= 0;
end else begin #20;
if (current_state != next_state) reset = 0;
counter <= 0;
else if (current_state != IDLE) #10;
counter <= counter + 1; start = 1;
current_state <= next_state; #10;

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end start = 0;
end
always @(*) begin #((120 + 1200 + 600 + 180 + 300 + 30) *
next_state = current_state; 10);
beep = 0; $display("Simulation Finished");
$finish;
case (current_state) end
IDLE: begin
if (start) endmodule
next_state = FILL;
end

FILL: begin
if (counter >= FILL_TIME)
next_state = WASH;
end
WASH: begin
if (counter >= WASH_TIME)
next_state = RINSE;
end
RINSE: begin
if (counter >= RINSE_TIME)
next_state = DRAIN;
end
DRAIN: begin
if (counter >= DRAIN_TIME)
next_state = SPIN;
end
SPIN: begin
if (counter >= SPIN_TIME)
next_state = DONE;
end
DONE: begin
beep = 1;
if (counter >= DONE_TIME)
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end

always @(*) begin


state = current_state;
end

endmodule

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Output

3) Design and Implement simple I2C bus Protocol using Verilog on Modelsim

Design Code
MASTER CONTROLLER

`timescale 1ns / 1ps

module i2c_controller(
input wire clk,
input wire rst,
input wire [6:0] addr,
input wire [7:0] data_in,
input wire enable,
input wire rw,

output reg [7:0] data_out,


output wire ready,

inout i2c_sda,
inout wire i2c_scl
);

localparam IDLE = 0;
localparam START = 1;
localparam ADDRESS = 2;
localparam READ_ACK = 3;
localparam WRITE_DATA = 4;
localparam WRITE_ACK = 5;
localparam READ_DATA = 6;
localparam READ_ACK2 = 7;
localparam STOP = 8;

localparam DIVIDE_BY = 4;

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reg [7:0] state;


reg [7:0] saved_addr;
reg [7:0] saved_data;
reg [7:0] counter;
reg [7:0] counter2 = 0;
reg write_enable;
reg sda_out;
reg i2c_scl_enable = 0;
reg i2c_clk = 1;

assign ready = ((rst == 0) && (state == IDLE)) ? 1 : 0;


assign i2c_scl = (i2c_scl_enable == 0 ) ? 1 : i2c_clk;
assign i2c_sda = (write_enable == 1) ? sda_out : 'bz;

always @(posedge clk) begin


if (counter2 == (DIVIDE_BY/2) - 1) begin
i2c_clk <= ~i2c_clk;
counter2 <= 0;
end
else counter2 <= counter2 + 1;
end

always @(negedge i2c_clk, posedge rst) begin


if(rst == 1) begin
i2c_scl_enable <= 0;
end else begin
if ((state == IDLE) || (state == START) || (state == STOP)) begin
i2c_scl_enable <= 0;
end else begin
i2c_scl_enable <= 1;
end
end

end

always @(posedge i2c_clk, posedge rst) begin


if(rst == 1) begin
state <= IDLE;
end
else begin
case(state)

IDLE: begin
if (enable) begin

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state <= START;


saved_addr <= {addr, rw};
saved_data <= data_in;
end
else state <= IDLE;
end

START: begin
counter <= 7;
state <= ADDRESS;
end

ADDRESS: begin
if (counter == 0) begin
state <= READ_ACK;
end else counter <= counter - 1;
end

READ_ACK: begin
if (i2c_sda == 0) begin
counter <= 7;
if(saved_addr[0] == 0) state <= WRITE_DATA;
else state <= READ_DATA;
end else state <= STOP;
end

WRITE_DATA: begin
if(counter == 0) begin
state <= READ_ACK2;
end else counter <= counter - 1;
end

READ_ACK2: begin
if ((i2c_sda == 0) && (enable == 1)) state <= IDLE;
else state <= STOP;
end

READ_DATA: begin
data_out[counter] <= i2c_sda;
if (counter == 0) state <= WRITE_ACK;
else counter <= counter - 1;
end

WRITE_ACK: begin
state <= STOP;
end

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STOP: begin
state <= IDLE;
end
endcase
end
end

always @(negedge i2c_clk, posedge rst) begin


if(rst == 1) begin
write_enable <= 1;
sda_out <= 1;
end else begin
case(state)

START: begin
write_enable <= 1;
sda_out <= 0;
end

ADDRESS: begin
sda_out <= saved_addr[counter];
end

READ_ACK: begin
write_enable <= 0;
end

WRITE_DATA: begin
write_enable <= 1;
sda_out <= saved_data[counter];
end

WRITE_ACK: begin
write_enable <= 1;
sda_out <= 0;
end

READ_DATA: begin
write_enable <= 0;
end

STOP: begin
write_enable <= 1;
sda_out <= 1;
end

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endcase
end
end

endmodule

SLAVE CONTROLLER

`timescale 1ns / 1ps

module i2c_slave_controller(
inout sda,
inout scl
);

localparam ADDRESS = 7'b0101010;

localparam READ_ADDR = 0;
localparam SEND_ACK = 1;
localparam READ_DATA = 2;
localparam WRITE_DATA = 3;
localparam SEND_ACK2 = 4;

reg [7:0] addr;


reg [7:0] counter;
reg [7:0] state = 0;
reg [7:0] data_in = 0;
reg [7:0] data_out = 8'b11001100;
reg sda_out = 0;
reg sda_in = 0;
reg start = 0;
reg write_enable = 0;

assign sda = (write_enable == 1) ? sda_out : 'bz;

always @(negedge sda) begin


if ((start == 0) && (scl == 1)) begin
start <= 1;
counter <= 7;
end
end

always @(posedge sda) begin


if ((start == 1) && (scl == 1)) begin

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state <= READ_ADDR;


start <= 0;
write_enable <= 0;
end
end

always @(posedge scl) begin


if (start == 1) begin
case(state)
READ_ADDR: begin
addr[counter] <= sda;
if(counter == 0) state <= SEND_ACK;
else counter <= counter - 1;
end

SEND_ACK: begin
if(addr[7:1] == ADDRESS) begin
counter <= 7;
if(addr[0] == 0) begin
state <= READ_DATA;
end
else state <= WRITE_DATA;
end
end

READ_DATA: begin
data_in[counter] <= sda;
if(counter == 0) begin
state <= SEND_ACK2;
end else counter <= counter - 1;
end

SEND_ACK2: begin
state <= READ_ADDR;
end

WRITE_DATA: begin
if(counter == 0) state <= READ_ADDR;
else counter <= counter - 1;
end

endcase
end
end

always @(negedge scl) begin

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case(state)

READ_ADDR: begin
write_enable <= 0;
end

SEND_ACK: begin
sda_out <= 0;
write_enable <= 1;
end

READ_DATA: begin
write_enable <= 0;
end

WRITE_DATA: begin
sda_out <= data_out[counter];
write_enable <= 1;
end

SEND_ACK2: begin
sda_out <= 0;
write_enable <= 1;
end
endcase
end
endmodule

TESTBENCH

`timescale 1ns / 1ps

module i2c_controller_tb;

// Inputs
reg clk;
reg rst;
reg [6:0] addr;
reg [7:0] data_in;
reg enable;
reg rw;

// Outputs
wire [7:0] data_out;
wire ready;

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// Bidirs
wire i2c_sda;
wire i2c_scl;

// Instantiate the Unit Under Test (UUT)


i2c_controller master (
.clk(clk),
.rst(rst),
.addr(addr),
.data_in(data_in),
.enable(enable),
.rw(rw),
.data_out(data_out),
.ready(ready),
.i2c_sda(i2c_sda),
.i2c_scl(i2c_scl)
);

i2c_slave_controller slave (
.sda(i2c_sda),
.scl(i2c_scl)
);

initial begin
clk = 0;
forever begin
clk = #1 ~clk;
end
end

initial begin
// Initialize Inputs
clk = 0;
rst = 1;

// Wait 100 ns for global reset to finish


#100;

// Add stimulus here


rst = 0;
addr = 7'b0101010;
data_in = 8'b10101010;
rw = 0;
enable = 1;

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#10;
enable = 0;

#500
$finish;

end
endmodule
Output

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