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HLS Assignment 1

The document details the design and implementation of a 4-bit magnitude comparator in Verilog, including structural and dataflow code, along with a testbench for simulation. It also covers the realization of a logical function using multiplexers and AND/OR gates, providing structural Verilog code and a truth table. The document includes examples of input combinations and expected outputs for both the magnitude comparator and the logical function.

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0% found this document useful (0 votes)

44 views11 pages

HLS Assignment 1

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karan2004sss

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HLS Assignment 1 2025

A]. A magnitude comparator checks if one number is greater than or equal to or less than
another number. A 4-bit magnitude comparator takes two 4-bit numbers, A and B, as input.
We write the bits in A and B as follows. The leftmost bit is the most significant bit. A =
A(3) A(2) A(1) A(0) B = B(3) B(2) B(1) B(0) The magnitude can be compared by
comparing the numbers bit by bit, starting with the most significant bit. If any bit
mismatches, the number with bit 0 is the lower number. To realize this functionality in
logic equations, let us define an intermediate variable. Notice that the function below is an
XNOR function. x(i) = A(i).B(i) + A(i)'.B(i)' The three outputs of the magnitude
comparator are A_gt_B, A_lt_B, A_eq_B. They are defined with the following logic
equations: A_gt_B = A(3).B(3)' + x(3).A(2).B(2)' + x(3).x(2).A(1).B(1)' +
x(3).x(2).x(1).A(0).B(0)' A_lt_B = A(3)'.B(3) + x(3).A(2)'.B(2) + x(3).x(2).A(1)'.B(1) +
x(3).x(2).x(1).A(0)'.B(0) A_eq_B = x(3).x(2).x(1).x(0) Write the Structural Verilog
description of the module magnitude_comparator using in built logic gates in Verilog.
Instantiate the magnitude comparator inside the stimulus module and try out a few
combinations of A and B.
Solution:
structural code:
`timescale 1ns / 1ps
module magnitude_comparator(
input [3:0] A, B,
output A_gt_B, A_lt_B, A_eq_B
);
wire [3:0] x;
wire [3:0] A_n, B_n;
wire [3:0] term_gt, term_lt;
wire [2:0] x1, x2;

xnor (x[3], A[3], B[3]);

xnor (x[2], A[2], B[2]);
xnor (x[1], A[1], B[1]);
xnor (x[0], A[0], B[0]);

// Inverts
not (A_n[3], A[3]); not (A_n[2], A[2]); not (A_n[1], A[1]); not (A_n[0], A[0]);
not (B_n[3], B[3]); not (B_n[2], B[2]); not (B_n[1], B[1]); not (B_n[0], B[0]);

// A_gt_B
and (term_gt[0], A[3], B_n[3]);
and (x1[0], x[3], A[2]); and (term_gt[1], x1[0], B_n[2]);
and (x1[1], x[3], x[2], A[1]); and (term_gt[2], x1[1], B_n[1]);
and (x1[2], x[3], x[2], x[1], A[0]); and (term_gt[3], x1[2], B_n[0]);

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HLS Assignment 1 2025

or (A_gt_B, term_gt[0], term_gt[1], term_gt[2], term_gt[3]);

// A_lt_B
and (term_lt[0], A_n[3], B[3]);
and (x2[0], x[3], A_n[2]); and (term_lt[1], x2[0], B[2]);
and (x2[1], x[3], x[2], A_n[1]); and (term_lt[2], x2[1], B[1]);
and (x2[2], x[3], x[2], x[1], A_n[0]); and (term_lt[3], x2[2], B[0]);
or (A_lt_B, term_lt[0], term_lt[1], term_lt[2], term_lt[3]);

// A_eq_B = x3 & x2 & x1 & x0

and (A_eq_B, x[3], x[2], x[1], x[0]);
endmodule

Testbench:

`timescale 1ns / 1ps

module stimulus;
reg [3:0] A, B;
wire A_gt_B, A_lt_B, A_eq_B;
magnitude_comparator uut (
.A(A),
.B(B),
.A_gt_B(A_gt_B),
.A_lt_B(A_lt_B),
.A_eq_B(A_eq_B)
);
initial begin
A = 4'b1100; B = 4'b1100; #10;
$display("A=%b, B=%b, GT=%b, LT=%b, EQ=%b", A, B, A_gt_B, A_lt_B,
A_eq_B);
A = 4'b1110; B = 4'b0111; #10;
$display("A=%b, B=%b, GT=%b, LT=%b, EQ=%b", A, B, A_gt_B, A_lt_B,
A_eq_B);
A = 4'b0001; B = 4'b0010; #10;
$display("A=%b, B=%b, GT=%b, LT=%b, EQ=%b", A, B, A_gt_B, A_lt_B,
A_eq_B);
A = 4'b1010; B = 4'b1001; #10;
$display("A=%b, B=%b, GT=%b, LT=%b, EQ=%b", A, B, A_gt_B, A_lt_B,
A_eq_B);
A = 4'b1111; B = 4'b0000; #10;
$display("A=%b, B=%b, GT=%b, LT=%b, EQ=%b", A, B, A_gt_B, A_lt_B,
A_eq_B);

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HLS Assignment 1 2025

$finish;
end
endmodule

Simulation Result:

Dataflow code :

`timescale 1ns / 1ps

module Comparator(
input [3:0] A,
input [3:0] B,
output A_eq_B,
output A_gt_B,
output A_lt_B
);
wire [3:0]x;
assign x = A ~^ B; // Bitwise XNOR (all bits in one line)
//A_gt_B = A(3).B(3)' + x(3).A(2).B(2)' + x(3).x(2).A(1).B(1)' +
x(3).x(2).x(1).A(0).B(0)'
assign A_gt_B = (A[3] & ~B[3]) |
(x[3] & A[2] & ~B[2]) |
(x[3] & x[2] & A[1] & ~B[1]) |
(x[3] & x[2] & x[1] & A[0] & ~B[0]);
//A_lt_B = A(3)'.B(3) + x(3).A(2)'.B(2) + x(3).x(2).A(1)'.B(1) +
x(3).x(2).x(1).A(0)'.B(0)
assign A_lt_B = (~A[3] & B[3]) |

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HLS Assignment 1 2025

(x[3] & ~A[2] & B[2]) |

(x[3] & x[2] & ~A[1] & B[1]) |
(x[3] & x[2] & x[1] & ~A[0] & B[0]);
// A_eq_B = x[3] & x[2] & x[1] & x[0]
assign A_eq_B = x[3] & x[2] & x[1] & x[0];
endmodule

Testbench:

`timescale 1ns / 1ps

module Comparator_tb();
reg [3:0] A, B;
wire A_eq_B, A_gt_B, A_lt_B;
Comparator uut (
.A(A),
.B(B),
.A_eq_B(A_eq_B),
.A_gt_B(A_gt_B),
.A_lt_B(A_lt_B)
);

initial begin

A = 4'b0000; B = 4'b0000; #10;

$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b1000; B = 4'b0001; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b0001; B = 4'b0010; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b1010; B = 4'b1001; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b1111; B = 4'b0000; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b0101; B = 4'b0110; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);

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HLS Assignment 1 2025

A = 4'b0111; B = 4'b1000; #10;

$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b1110; B = 4'b1111; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b1110; B = 4'b0110; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b0111; B = 4'b0110; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);
A = 4'b0111; B = 4'b0111; #10;
$display("A=%b, B=%b, EQ=%b, GT=%b, LT=%b", A, B, A_eq_B, A_gt_B,
A_lt_B);

$finish;
end
endmodule

Simulation Result:

B]. Show how the function, f = w1!w3! + w1w3 + w2w3 + w1w2, can be realized using
one or more instances of the circuit in Figure P4.1. Note that there are no NOT gates in the
circuit; hence complements of signals have to be generated using the multiplexers in the
logic block. Write the Structural Verilog description of your implementation using
Behavioral Verilog description of the circuit shown in Figure P4.1. Instantiate your

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HLS Assignment 1 2025

implementation inside the stimulus or the test bench module and try out all combinations
of the inputs w1, w2 and w3, respectively.

Solution:
Truth table:

w1 w2 w3 f
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Structural code:
`timescale 1ns / 1ps

module and4 (input a, b, c, d, output y);

wire t1, t2;
and(t1, a, b);
and(t2, c, d);
and(y, t1, t2);
endmodule

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HLS Assignment 1 2025

module or8 (input a, b, c, d, e, f, g, h, output y);

wire t1, t2, t3, t4, t5, t6;
or(t1, a, b);
or(t2, t1, c);
or(t3, t2, d);
or(t4, t3, e);
or(t5, t4, f);
or(t6, t5, g);
or(y, t6, h);
endmodule

module mux_logic_block1 (
input w1, w2, w3,
input i1, i2, i3, i4, i5, i6, i7, i8,
output f
);
wire t1, t2, t3, t4, t5, t6, t7, t8;
wire nw1, nw2, nw3;
not(nw1, w1);
not(nw2, w2);
not(nw3, w3);

and4 a1(nw1, nw2, nw3, i1, t1);

and4 a2(nw1, nw2, w3, i2, t2);
and4 a3(nw1, w2, nw3, i3, t3);
and4 a4(nw1, w2, w3, i4, t4);
and4 a5( w1, nw2, nw3, i5, t5);
and4 a6( w1, nw2, w3, i6, t6);
and4 a7( w1, w2, nw3, i7, t7);
and4 a8( w1, w2, w3, i8, t8);

or8 o1(t1, t2, t3, t4, t5, t6, t7, t8, f);
endmodule

module function_implementation1 (
input w1, w2, w3,
output f
);
mux_logic_block1 mux (
.w1(w1),
.w2(w2),

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HLS Assignment 1 2025

.w3(w3),
.i1(1'b1),
.i2(1'b0),
.i3(1'b1),
.i4(1'b1),
.i5(1'b0),
.i6(1'b1),
.i7(1'b1),
.i8(1'b1),
.f(f)
);
endmodule

Testbench:
`timescale 1ns / 1ps

module tb_function_implementation1();
reg w1, w2, w3;
wire f;
function_implementation1 uut (
.w1(w1),
.w2(w2),
.w3(w3),
.f(f)
);
initial begin
w1 = 0;
w2 = 0;
w3 = 0;
$display("Time\tw1 w2 w3 | f");
$display("------------------");