©2008, Dr. Meeta Yadav, www4.ncsu.

edu/~myadav/Research 1

Topics

• Data Types
• Fixed Size Arrays
• Dynamic Arrays
• Queues
• Associative Arrays
• Array Methods
• Structures
• Enumerated Types
• Strings

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 2

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 SystemVerilog Data Types
 Literal value assignments in Verilog
• In verilog a vector can be easily filled with all Xs, all Zs or all zeros

parameter SIZE=64;
reg [SIZE-1:0] data;
data=0; Fills all bits of data with zero
data=‘bz; Fills all bits of data with Zs
data=‘bx; Fills all bits of data with Xs
data=64’hFFFFFFFFFFFFFFFF; Fills all bits of data with 1s
Filling a vector with literal value in Verilog

Redefine size to 128 and fill the vector with 0s,Zs,Xs and 1s

parameter SIZE=128;
reg [SIZE-1:0] data;
data=0; Fills all bits of data with zero
data=‘bz; Fills all bits of data with Zs
data=‘bx; Fills all bits of data with Xs
data=128’hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; Fills all bits of data with 1s
Filling a vector with literal value by changing the size in Verilog

Each of the assignments in the above example are scalable except filling the vector will all ones

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 3

SystemVerilog Overview

• New data types

 Two-state: better performance, reduced memory usage
 Queues, dynamic and associative arrays and automatic storage:
reduced memory usage, built in support for searching and sorting
 Unions and packed structures: allows multiple views of the same data
 Classes and structures: support for abstract data structures
 Strings: built in string support
 Enumerated types: code is easier to write and understand

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 4

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 SystemVerilog Data Types
 Literal value assignments in SystemVerilog
• SystemVerilog enhances assignment of a literal value in two ways:
 Allows specifying a fill value without having to specify a radix of binary, octal or
hexadecimal
 The fill value can also be a logic 1

parameter SIZE=64;
logic [SIZE-1:0] data;
data=‘0; Fills all bits of data with zero
data=‘z; Fills all bits of data with z
data=‘x; Fills all bits of data with x
data=‘1; Fills all bits of data with 1s
Filling a vector with literal value in SystemVerilog

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 5

SystemVerilog Built in Data Types

• The 4-state logic type
 Verilog has two basic data types: wires and regs
► Verilog uses reg type as a general purpose variable for modeling hardware behavior
in initial and always procedural blocks
– Context of use of reg determines if the hardware represented is combinational logic or
sequential
► Verilog uses wire to connect different parts of the design
 SystemVerilog uses the more intuitive logic keyword to represent a general
purpose, hardware centric data-type
► Can be driven by continuous assignments, gates and modules
► Cannot have multiple drivers (for example for a bidirectional bus use a wire)

reg is replaced by logic

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 6

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 SystemVerilog Built in Data Types
• The 4-state logic type
 Logic has 4 states
States are 0,1,z,x
logic [31:0] r; // 4-states

 Some example declarations using the logic type

logic resetN; //a 1-bit wide 4-state variable

logic [63:0] Data; //a 64-bit wide variable
logic [0:7] Array [0:255];//an array of 8-bit variables

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 7

SystemVerilog Data Types

 Two state data types : bit, byte, shortint, int, longint

• Can only have two states 0 or 1 (x and z are mapped to a 0)
• Used to improve simulation performance and reduce memory usage
• Keep away from the DUT (since x or z values are converted to a 0 or 1)

Type Description Example

bit User defined size, unsigned bit b; bit [31:0] b32;
byte 8 bits, signed byte b8;
shortint 16 bits, signed shortint s;
int 32 bits, signed int i;
longint 64 bits, signed longint l;

logic [7:0] x
no
Are they the same? (Byte is signed so can count up
to 127 and not 255 as might be
byte x expected)

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 8

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 SystemVerilog Data Types
 Two state simulation semantics
• 4-state begins simulation with x and a 2-state begins simulations with a 0
• 2-state variables cannot represent an uninitialized state
• Can legally assign 4-state values to 2-state variables. X and Z values are mapped
to 0 in two state types
• Use $isunknown operator to check if any bit of an expression is x or z

logic a; bit b;
a=b; x or z values get converted to a logic “0”

“$isunknown” operator returns 1 if any bit of the expression is x or z

example:
if($isunknown(iport)==1 Returns a “1” on detecting an x or a z (can be any bit)
$display (“ 4-state variable detected”);

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 9

Synthesis Guidelines
• Two state simulation semantics
 SystemVerilog 2-state to 4-state mapping is standardized
► Different simulators map different values
► Some commercial simulators map x to a 0 whereas some map x to a 1
► SV maps x to 0 and is tool independent
 SystemVerilog 2-state initialization is standardized
► Some simulators map 4-state x initial value to a 0 and generate an event
whereas others don’t causing values sensitive to negative edge transitions
to change
► SV 2-state variable begins simulation with a value of 0 without causing any
events
 SystemVerilog 2-state is standardized
► casez and casex descision statements can be affected by 2-state
simulation models. casez treats Zs as don’t cares and casex treats Zs and
Xs as don’t cares

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 10

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 Synthesis Guidelines

• Using 2-state types with case statements

case (State)
RESET: Next = WAITE;
WAITE: Next = LOAD;
LOAD: Next = DONE;
DONE: Next = WAITE;
default: Next = 4’bx; // unknown state
endcase

Simulation: default assignment of logic x would result in a run-time error

Synthesis: treats it as a special flag, indicating that, for any condition not covered by the
other case selection items, the output value is don’t care

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 11

Synthesis Guidelines
• Synthesis guidelines for data types
 The 4-state logic type and 2-state bit, byte, shortint, int and longint types are
synthesizable
 2-state types synthesize the same as 4-state types
 Synthesis ignores the default initial value of 2-state types
► 2-state types begin simulation with a default value of 0
► The post synthesis design is not guaranteed to power up with zeros the same way
as pre-synthesis models using 2-state variables

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 12

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 Fixed Size Arrays
 Fixed Size Arrays
 Multiple dimensions supported
 Out-of-bounds write ignored
 Out-of-bounds read returns x, even for 2-state

 byte, shortints and ints are stored in a single longword

 longint is stored in two longwords

type name [constant];

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 13

Fixed Size Arrays

 Single Dimension Array
31 0
int lo_hi[0:15]; //16 ints [0]..[15] lo_hi[0]
int lo_hi[16]; //16 ints [0].. lo_hi[1]
[15]
...

lo_hi[15]

32 bits width
 Multidimensional Array
[0,0] [0,1] [0,2] [0,3]
[1,0] [1,1] [1,2] [1,3]
int array [0:7][0:3]; //Verbose Declaration [2,0] [2,1] [2,2] [2,3]
int array [8][4]; //Compact Declaration
[3,0] [3,1] [3,2] [3,3]
array[7][3]=1;
.. .. .. ..
. . . .
[7,0] [7,1] [7,2] [7,3]

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 14

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 Fixed Size Arrays
 Fixed Size Arrays / Unpacked Arrays
• Fixed Size arrays are stored on a longword boundary (32 bits)

bit [7:0] up_array[3];

unused space 7 65 4 3 21 0
up_array[0]
up_array[1]
up_array[2]

Total memory consumed = 3*32 = 96 bits

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 15

Fixed Size Arrays

 Fixed Size Arrays / Unpacked Arrays

up_array[0]=‘0;
up_array[1]=‘1;
up_array[2]=‘0;
up_array[2][3]=1;

unused space 7 65 4 3 21 0
up_array[0] 0 00 0 0 00 0
up_array[1] 1 11 1 1 11 1
up_array[2] 0 00 0 1
0 00 0

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 16

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 Fixed Size Arrays
 Quiz

bit[16:1] b_unpack [1:3];

b_unpack[0]=‘0; Out of bound writes are ignored
b_unpack[1]=‘0;
b_unpack[2]=‘1;
b_unpack[3]=‘0;
b_unpack [1][1]=b_unpack [2][3];
b_unpack [3][16]=1;
i=b_unpack [3][0]; Out of bound reads return x

unused space 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1

b_unpack[1] 0 00 0 0 00 0 0 00 0 0 0010
b_unpack[2] 1 11 1 1 11 1 1 11 1 1 11 1
b_unpack[3] 0 00 0 0 00 0 0 00 0 0 00 0
1

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 17

Fixed Size Arrays

 Simplified unpacked array declaration
int array[20]; int array[64:83];
an array with elements from 0 to 19 an array with addresses 64 to 83
32 bits 32 bits
0 64
1 65
2 66
. .
. .
. .
19 83

logic [31:0] data [1024]; logic [32] d;

32 bit wide array with 0 to 1023 elements Not an array
32 bits
0 32 bits wide vector
1
2
.
.
.
1023
©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 18

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 Fixed Size Arrays: Initializing Unpacked Arrays
 The array literal ‘{ }, ‘n{ }
 Can initialize all or some values
int array1 [4]=‘{3,2,4,2}; array1 [0:2] =‘{5,6,7};
array1 array1

0 3 0 3
5
1 2 1 2
6
2 4 2 4
7
3 2 3 2
32 bits 32 bits

array1 = ‘{{3}, ‘{3{8}}}; int md [2][3]=‘{‘{0,1,2}, ‘{3,4,5}};

array1

35 md

86
0 1 2
87
3 4 5
82
32bits 32bits 32bits
32 bits

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 19

Basic Array Operations

• for Operation
 Most common way of manipulating an array
 Variable i is declared local to the for loop Returns
i is local to size of
 $size returns the size of the array the for loop array

initial begin
bit [31:0] src[5], dst[5];
for (int i=0; i<$size(src); i++)
src[i]=i;
dst[i]=i*2;
end
src dst

0 0 0 0
1 1 1 2
2 2 2 4
3 3 3 6
4 4 4 8
32bits 32bits

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 20

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 Basic Array Operations
 foreach Operation
 Specify the array name and index in square brackets and SystemVerilog
steps through each element
 The index variable is automatically declared and is local to the loop

initial begin src dst

bit [31:0] src[5], dst[5]; 0 0
0 0
int md[2][3];
1 1 1 3
foreach(src[i])
src[i]=i; 2 2 2 6
foreach(dst[j]) 3 9
3 3
dst[j]=src[j]*2+j;
foreach (md[i,j]); 4 4 4 12
md[i,j]=2*i+j; 32bits 32bits
end

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 21

Basic Array Operations

 foreach Operation
initial begin
bit [31:0] src[5], dst[5];
int md[2][3];
foreach(src[i])
src[i]=i;
foreach(dst[j])
dst[j]=src[j]*2+j;
foreach (md[i,j]);
md[i,j]=2*i+j;
end

md[0,0] md[0,1] md[0,2]

md[0] 0 1 2

md[1,0] md[1,1] md[1,2]

md[1] 2 3 4

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 22

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 Basic Array Operations
 Copy and Compare
• Can perform copy and compare without loops (only == and != operations)
• Cannot perform aggregate arithmetic operations such as addition on arrays

initial begin
compare bit [31:0] src[5] = ‘{0,1,2,3,4},
operation dst[5] = ‘{5,4,3,2,1};
if(src==dst) src dst
$display(“src==dst”);
0 5 0 0
5
else 0
copy $display(“src!=dst”);
operation 1 1 1 1
4
dst=src;
src[0]=5; 2 2 2 32
if(src[1:4]==dst[1:4])
$display(“src==dst”); 3 3 2
3
3
else
$display(“src!=dst”); 4 1
4
4 4
end
32bits 32bits

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 23

Basic Array Operations

 Bit and Array subscripts

initial begin
bit [31:0] src[5] = ‘{5{5}},
$displayb(src[0], src[0][0],src[0][2:1]);
end

src src[0][0]=1

0 00000000000000000000000000000101 src[0]=5
1 00000000000000000000000000000101
2 00000000000000000000000000000101 src[2][2:1]=10
3 00000000000000000000000000000101
4 00000000000000000000000000000101

32bits

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 24

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 Packed Arrays
• Packed array
 Treated as a both an array and a single value
 Stored as contiguous bits
 Packed bit and word dimensions should be specified
 Dimensions must be specified in [lo:hi] format

bit [3:0][7:0]bytes;
bytes=32’habcd_efab;
$displayh(bytes
bytes[3]
bytes[3][7]);
bytes[3][7]=1
7 65 4 3 21 0 7 65 4 3 21 0 7 65 4 3 21 0 7 65 4 3 21 0

bytes 1 01 1 1 01 0 1 11 1 1 11 0 1 10 1 1 10 0 1 01 1 1 01 0
b a f e d c b a
Bytes=abcdefab
bytes[3]=ab

bytes: Shows all 32 bits //abcd_efab

bytes[3]: shows the most significant byte //ab
bytes[3][7]: shows the most significant bit //1

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 25

Packed Array
• Packed array initialization
 Packed arrays can be initialized at declaration using simple assignments
 The assignment can be a constant value, a concatenation of constant values
or a replication of constant values

logic [3:0][7:0] a = 32’h0; Vector assignment

logic [3:0][7:0] b = {16’hz, 16’h0}; Concatenate operator
logic [3:0][7:0] c = {16{2’b01}}; Replicate operator

7 65 4 3 21 0 7 65 4 3 21 0 7 65 4 3 21 0 7 65 4 3 21 0
0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0 0 00 0
z zz z z zz z z zz z z zz z 0 00 0 0 00 0 0 00 0 0 00 0
0 10 1 0 10 1 0 10 1 0 10 1 0 10 1 0 10 1 0 10 1 0 10 1

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 26

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 Mixed Arrays
• Mixing packed and unpacked array
 Common to have combination of packed and unpacked array
 p_array is an unpacked array of three packed elements
 which dimension is unpacked? bit [3:0][7:0]p_array[0:2];

p_array[0][3] p_array[0][1][6]

p_array[0] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
p_array[1] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
p_array[2] 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

 Unpacked array
bit [7:0] up_array[3];

unused space
up_array[0] 7 65 4 3 21 0
up_array[1] 7 65 4 3 21 0
up_array[2] 7 65 4 3 21 0

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 27

Mixed Arrays
• Indexing arrays of arrays
 When indexing mixed arrays, unpacked dimensions are referenced first from the left-
most to the right-most dimension
 Packed dimensions are referenced second from the left-most dimension to the right-
most dimension

logic [3:0][7:0] mixed_array [0:7] [0:7] [0:7];

mixed_array [0] [1] [2] [3] [4] = 1’b1;

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 28

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 Packed vs Unpacked Arrays

• Using packed or unpacked arrays

 Packed arrays are handy to convert to and from scalars
 Helpful in referencing memory as a byte or a longword
 If you need to wait for a change in an array, you have to use a packed array
 Only fixed arrays can be packed
 Dynamic arrays, associative arrays and queues cannot be packed

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 29

Quiz

• What is the basic difference between logic and reg?

 There is no difference!
• What is the difference between logic and bit?
 logic is 4-state, bit is 2-state
• Should the 2-state variable be used with the DUT? Why?
 No, because it converts x and z values to 0
• bit[31:0] src[5]=‘{‘{5,6,7},’{2{5}}}
src[1]= 110
src[3][0]= 1
src[2][3:1]= 011

©2008, Dr. Meeta Yadav, www4.ncsu.edu/~myadav/Research 30

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