VLSI LAB REPORT
Experiment No. 01: Design of Comparator Circuit in VLSI
Objective:
To design and simulate a 2-bit comparator circuit using VHDL and understand its working
through behavioral modeling and waveform analysis.
Apparatus/Software Required:
Computer with VLSI simulation tools (ModelSim, Xilinx ISE, or Vivado)
VHDL Programming Environment
Basic knowledge of digital logic and combinational circuits
Theory:
A comparator is a digital logic circuit that compares two binary numbers and determines their
equality or relational status.
For 2-bit comparator, given two inputs A and B (each 2 bits wide), the outputs are:
A = B → Equal
A > B → Greater
A < B → Smaller
Truth Table:
A (A1 A0) B (B1 B0) A=B A>B A<B
00 00 1 0 0
01 00 0 1 0
01 01 1 0 0
10 01 0 1 0
01 10 0 0 1
11 11 1 0 0
VHDL Code for 2-bit Comparator:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator_2bit is
Port (
A : in STD_LOGIC_VECTOR (1 downto 0);
B : in STD_LOGIC_VECTOR (1 downto 0);
A_equal_B : out STD_LOGIC;
A_greater_B : out STD_LOGIC;
A_less_B : out STD_LOGIC
);
end comparator_2bit;
architecture Behavioral of comparator_2bit is
begin
process (A, B)
begin
if A = B then
A_equal_B <= '1';
A_greater_B <= '0';
A_less_B <= '0';
elsif A > B then
A_equal_B <= '0';
A_greater_B <= '1';
A_less_B <= '0';
else
A_equal_B <= '0';
A_greater_B <= '0';
A_less_B <= '1';
end if;
end process;
end Behavioral;
Procedure:
1. Open the VHDL simulator (ModelSim/Vivado).
2. Create a new project and add the above VHDL code.
3. Compile the design.
4. Write a testbench to apply all combinations of inputs (A and B).
5. Simulate the design.
6. Observe the output waveform for each input combination.
7. Verify the outputs for A = B, A > B, and A < B.
Sample Observation Table:
A (Binary) B (Binary) A=B A>B A<B
00 00 1 0 0
01 00 0 1 0
10 11 0 0 1
11 10 0 1 0
11 11 1 0 0
Result:
The 2-bit comparator circuit was successfully designed and simulated.
All outputs were verified and matched the expected truth table.
The comparator correctly identified when A = B, A > B, and A < B.
Conclusion:
This experiment demonstrated the design and simulation of a comparator circuit in VHDL. It
helped in understanding how to compare two binary values and produce logical outputs
accordingly. Such comparators are fundamental components in ALUs, CPUs, and control units,
and this lab strengthens concepts in behavioral modeling, condition checking, and
combinational circuit design.
Experiment No. 02: Design of Multiplexer (MUX) Circuit in VHDL
Objective:
To design and simulate a 4-to-1 multiplexer (MUX) circuit using VHDL and understand its
operation through behavioral modeling and simulation.
Apparatus/Software Required:
Computer with VHDL tools (ModelSim / Vivado / Xilinx ISE)
VHDL Programming Environment
Basic knowledge of logic gates and multiplexers
Theory:
A multiplexer (MUX) is a combinational circuit that selects one of many input signals and
forwards it to a single output line, based on selection inputs.
A 4-to-1 multiplexer has:
4 input lines: I0, I1, I2, I3
2 selection lines: S1, S0
1 output line: Y
Truth Table of 4:1 MUX
S1 S0 Output (Y)
0 0 I0
0 1 I1
1 0 I2
1 1 I3
VHDL Code for 4-to-1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1 is
Port (
I0, I1, I2, I3 : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(1 downto 0);
Y : out STD_LOGIC
);
end mux4to1;
architecture Behavioral of mux4to1 is
begin
process(I0, I1, I2, I3, S)
begin
case S is
when "00" =>
Y <= I0;
when "01" =>
Y <= I1;
when "10" =>
Y <= I2;
when "11" =>
Y <= I3;
when others =>
Y <= '0';
end case;
end process;
end Behavioral;
Procedure:
1. Launch the VHDL simulation tool (ModelSim, Vivado, etc.).
2. Create a new project and add the above MUX VHDL code.
3. Compile the design.
4. Write a testbench to apply all input combinations of selection lines and inputs.
5. Simulate the design and observe the output waveform.
6. Confirm that the correct input appears on the output based on the selection line.
Observation Table:
S1 S0 I3 I2 I1 I0 Output (Y)
0 0 x x x 1 1
0 1 x x 0 x 0
1 0 x 1 x x 1
1 1 0 x x x 0
Result:
The 4-to-1 multiplexer was successfully designed and simulated in VHDL.
The output matched the selected input based on the value of the selection lines.
Conclusion:
This experiment demonstrated the working of a 4-to-1 multiplexer. The MUX selects one of the
four data inputs based on the two selection lines and routes it to the output. Multiplexers are
essential components in data routing, communication systems, and microprocessor designs.
This lab provided valuable experience in behavioral modeling and simulation using VHDL.
Experiment No. 03: Design of Encoder Circuit in VHDL
Objective:
To design and simulate a 4-to-2 priority encoder circuit using VHDL and verify its correct
operation through simulation.
Apparatus/Software Required:
VHDL simulator (ModelSim, Vivado, or Xilinx ISE)
Computer with VHDL toolchain
Basic understanding of combinational logic and encoder operation
Theory:
An encoder is a combinational circuit that converts 2ⁿ input lines into n-bit output lines. A
priority encoder ensures that when multiple inputs are active, the one with the highest priority
is encoded.
In a 4-to-2 priority encoder, there are:
4 input lines: I3 (highest priority), I2, I1, I0 (lowest priority)
2 output lines: Y1, Y0
Valid output (V): Indicates if any input is active
Truth Table of 4-to-2 Priority Encoder:
I3 I2 I1 I0 Y1 Y0 Valid (V)
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1
VHDL Code: 4-to-2 Priority Encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity priority_encoder_4to2 is
Port (
I : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(1 downto 0);
V : out STD_LOGIC
);
end priority_encoder_4to2;
architecture Behavioral of priority_encoder_4to2 is
begin
process(I)
begin
if I(3) = '1' then
Y <= "11";
V <= '1';
elsif I(2) = '1' then
Y <= "10";
V <= '1';
elsif I(1) = '1' then
Y <= "01";
V <= '1';
elsif I(0) = '1' then
Y <= "00";
V <= '1';
else
Y <= "00";
V <= '0';
end if;
end process;
end Behavioral;
Procedure:
1. Open VHDL simulation tool (e.g., ModelSim or Vivado).
2. Create a new project and add the VHDL source code for the priority encoder.
3. Write a testbench to apply all input combinations.
4. Simulate the design and observe the outputs (Y1, Y0) and valid bit (V).
5. Compare simulated outputs with the truth table.
Observation Table:
I3 I2 I1 I0 Output (Y1 Y0) Valid (V)
0 0 0 0 00 0
0 0 0 1 00 1
0 0 1 0 01 1
0 1 0 0 10 1
1 0 0 0 11 1
Result:
The 4-to-2 priority encoder was successfully designed and simulated using VHDL. The outputs
matched the expected results according to the encoder truth table.
Conclusion:
This experiment demonstrated the design and simulation of a priority encoder using VHDL.
The encoder correctly outputs the binary code of the highest-priority active input, along with a
valid bit. This is a fundamental building block in digital systems, data routing, interrupt
handling, and more.
Experiment No. 04: Design of a 4-Bit Binary Counter Using VHDL
Objective:
To design and simulate a 4-bit binary up counter using VHDL and understand how
synchronous sequential circuits operate using flip-flops and clock signals.
Apparatus/Software Required:
Computer with VHDL simulation tools (ModelSim, Vivado, or Xilinx ISE)
VHDL Editor
Basic knowledge of digital electronics and sequential logic design
Theory:
A counter is a sequential circuit that counts clock pulses. A 4-bit binary counter counts from
0000 (decimal 0) to 1111 (decimal 15), and then rolls over to 0000.
It has:
4 output bits: representing the current count
Clock input: to increment the counter on each rising edge
Reset input: to initialize the counter to zero
Applications of Counters:
Timers and clocks
Frequency dividers
Event counting
Digital electronics and microcontrollers
VHDL Code: 4-bit Binary Up Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_4bit is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);
end counter_4bit;
architecture Behavioral of counter_4bit is
signal count : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
process(clk, reset)
begin
if reset = '1' then
count <= "0000";
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;
Q <= count;
end Behavioral;
Procedure:
1. Open the VHDL simulation software (ModelSim/Vivado).
2. Create a new project and add the VHDL source code.
3. Write a testbench to provide clock and reset inputs.
4. Simulate the counter for at least 16 clock cycles.
5. Observe the output signal Q.
6. Verify the binary count from 0 to 15 and reset behavior.
Observation Table (Simulation Example):
Clock Cycle Output Q (Binary) Decimal
0 0000 0
1 0001 1
2 0010 2
3 0011 3
... ... ...
15 1111 15
16 0000 0 (Rollover)
Result:
A 4-bit binary up counter was successfully designed and simulated using VHDL.
The output followed the expected binary sequence from 0 to 15.
The counter rolled over correctly after reaching the maximum value.
Conclusion:
This lab demonstrated the design of a synchronous 4-bit up counter using VHDL. The counter
increments its output on every rising clock edge and resets to 0 when the reset is active.
Understanding this basic sequential circuit is essential for building more advanced digital
systems like timers, state machines, and counters in processors.
Experiment No. 05: Design of Arithmetic and Logic Unit (ALU) in VHDL
Objective:
To design and simulate a 4-bit Arithmetic and Logic Unit (ALU) in VHDL that performs basic
arithmetic and logic operations based on a select/control input.
Apparatus/Software Required:
VHDL Simulation Tool (ModelSim / Vivado / Xilinx ISE)
Computer with VHDL programming environment
Basic knowledge of digital logic design and VHDL
Theory:
An Arithmetic and Logic Unit (ALU) is a digital circuit that performs arithmetic operations
(like addition, subtraction) and logic operations (like AND, OR, XOR, NOT) on binary
numbers.
In this experiment, the ALU takes:
Two 4-bit inputs (A and B)
One 3-bit selection input (Sel) to choose the operation
One 4-bit output (Result) and
Optional carry-out flag
ALU Operations Defined in This Experiment:
Sel Code Operation Description
000 A+B Addition
001 A-B Subtraction
010 A AND B Bitwise AND
011 A OR B Bitwise OR
100 A XOR B Bitwise XOR
101 NOT A Bitwise NOT (A only)
110 Increment A A + 1
111 Decrement A A - 1
VHDL Code: 4-Bit ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU_4bit is
Port (
A : in UNSIGNED(3 downto 0);
B : in UNSIGNED(3 downto 0);
Sel : in STD_LOGIC_VECTOR(2 downto 0);
Result : out UNSIGNED(3 downto 0);
Cout : out STD_LOGIC
);
end ALU_4bit;
architecture Behavioral of ALU_4bit is
signal temp : UNSIGNED(4 downto 0);
begin
process(A, B, Sel)
begin
case Sel is
when "000" => -- A + B
temp := ('0' & A) + ('0' & B);
Result <= temp(3 downto 0);
Cout <= temp(4);
when "001" => -- A - B
temp := ('0' & A) - ('0' & B);
Result <= temp(3 downto 0);
Cout <= temp(4);
when "010" => -- A AND B
Result <= A and B;
Cout <= '0';
when "011" => -- A OR B
Result <= A or B;
Cout <= '0';
when "100" => -- A XOR B
Result <= A xor B;
Cout <= '0';
when "101" => -- NOT A
Result <= not A;
Cout <= '0';
when "110" => -- Increment A
temp := ('0' & A) + 1;
Result <= temp(3 downto 0);
Cout <= temp(4);
when "111" => -- Decrement A
temp := ('0' & A) - 1;
Result <= temp(3 downto 0);
Cout <= temp(4);
when others =>
Result <= (others => '0');
Cout <= '0';
end case;
end process;
end Behavioral;
Procedure:
1. Open the VHDL simulation tool (e.g., ModelSim or Vivado).
2. Create a new project and add the ALU VHDL code.
3. Compile the design.
4. Create a testbench to apply different values of A, B, and Sel.
5. Simulate the design and verify the output (Result) for each operation.
6. Match simulation outputs with expected results.
Sample Observation Table:
A B Sel Operation Result Cout
0101 0011 000 A+B 1000 0
0101 0011 001 A B 0010 0
0101 0011 010 A AND B 0001 0
0101 0011 011 A OR B 0111 0
0101 0011 100 A XOR B 0110 0
0101 XXXX 101 NOT A 1010 0
0101 XXXX 110 Increment 0110 0
A
0101 XXXX 111 Decrement 0100 0
A
Result:
The 4-bit ALU was successfully designed and simulated using VHDL. All defined arithmetic
and logic operations were verified and performed correctly according to the selection input.
Conclusion:
This experiment demonstrated the design and implementation of an Arithmetic and Logic
Unit (ALU) in VHDL. The ALU performed a variety of arithmetic and logical operations based
on select inputs. The design improves understanding of combinational logic, case statements,
and modular digital design.
