EXPERIMENT NO.
AIM: Write a VHDL program to implement a 1:8 Demultiplexer
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
Demultiplexer means one to many. A demultiplexer is a circuit with one input
and many output. By applying control signal, we can steer any input to the
output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16
demultiplexer. Following figure illustrate the general idea of a demultiplexer
with 1 input signal, m control signals, and n output signals.
Application: The main application area of demultiplexer is communication
system, ALU, serial to parallel converter.
Truth Table:
VHDL Code :
Behavioral Modelling
entity Demultiplexer is
Port ( x : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (2 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end Demultiplexer;
architecture Behavioral of Demultiplexer is
begin
PROCESS (x,s)
BEGIN
case s IS
WHEN "000" => y<="0000000"&x;
WHEN "001" => y<="000000"&x&"0";
WHEN "010" => y<="00000"&x&"00";
WHEN "011" => y<="0000"&x&"000";
WHEN "100" => y<="000"&x&"0000";
WHEN "101" => y<="00"&x&"00000";
WHEN "110" => y<="0"&x&"000000";
WHEN "111" => y<=x&"0000000";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL codes of 1:8Demultiplexer is simulated & synthesized.
EXPERIMENT NO. 4
AIM: Write a VHDL program to implement 4 bit addition/subtraction
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
A full adder is a combinational circuit that forms the arithmetic sum of three
bits. It consists of three inputs and two outputs. Two of the inputs variables
represent the two significant bits to be added. The third input represents the
carry from the previous lower significant position. The two outputs are
designated by the symbols S for sum and C for carry. The binary variable S
gives the value of the least significant bit of the sum. The binary variable C
gives the output carry. The output variables are determined from the arithmetic
sum of the input bits.
A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adder connected in cascade, the
output carry from each full adder connected to the input carry of the next full
adder in the chain. Figure 4.1 shows the interconnection of four full adder (FA)
circuits to provide a 4-bit binary ripple carry adder. The augend bits of A and
addend bits of B are designated by subscript numbers from right to left, with
subscript 0denoting the least significant bit. The carries are connected in the
chain through the full adders. The input carry to the adder is C0 and it ripples
through the full adder to the output carry C4.The S output generate the required
sum bits. Application: The main application area of demultiplexer is
communication system, ALU, serial to parallel converter.
The 4bit adder is a typical example of a standard component. It can be used in
many applications involving arithmetic operations. Observe that the design of
this circuit by the classical method would require a truth table with 29 = 512
entries, since there are nine inputs to the circuit. By using an iterative method
of cascading a standard function, it is possible to obtain a simple and
straightforward implementation.
Fig: 4.1 Bit Adder
Binary Subtractor:
The subtraction of unsigned binary numbers can be done most conveniently by
means of complement. Subtraction A–B can be done by tacking the 2’s
complement of B and adding it to A. The 2’s complement can be obtained by
taking the 1’s complement and adding one to the least significant pair of bits. The
1’s complement can be implemented with the inverters and a one can be added to
the sum through the input carry as shown in figure4.2.
Fig: 4.2 Bit Subtractor
VHDL Code :
FullAdder.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end FullAdder;
architecture Behavioral of FullAdder is
begin
process(a,b,cin)
begin
s <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (cin and a);
end process;
end Behavioral;
FourBitAdder.vhd:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FourBitAdder is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
carryin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
carryout : out STD_LOGIC);
end FourBitAdder;
architecture Behavioral of FourBitAdder is
component fulladder is
port(
a,b,cin:in std_logic;
s,cout:out std_logic
);
end component;
signal c_int: std_logic_vector(2 downto 0);
begin
c1:fulladder port map(x(0),y(0),carryin,sum(0),c_int(0));
c2:fulladder port map(x(1),y(1),c_int(0),sum(1),c_int(1));
c3:fulladder port map(x(2),y(2),c_int(1),sum(2),c_int(2));
c4:fulladder port map(x(3),y(3),c_int(2),sum(3),carryout);
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL codes of implement 4 bit addition/subtraction is simulated &verified.
EXPERIMENT NO. 5
AIM: Write a program to implement 4- bit Comparator
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
A digital comparator is a hardware electronic device that takes two numbers as
input in binary form and determines whether one number is greater than, less
than or equal to the other number.
Fig: 4-Bit Comparator
It can be used to compare two four-bit words. The two 4-bit numbers are A =
A3 A2 A1 A0 and B3 B2 B1 B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number
and produces one of the following outputs as A = B, A < B and A>B. The
output logic statements of this converter are
Boolean Expression
• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or
• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 =
0, then A>B. Or
• If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal,
and if A0 = 1 and B0 = 0, then A > B.
• the output A > B logic expression can be written as
• The equal output is produced when all the individual bits of one number
are exactly coincides with corresponding bits of another number. Then the
logical expression for A=B output can be written as
• E = (A3 Ex-NOR B3) (A2 Ex-NOR B2) (A1 Ex-NOR B1) (A0 Ex-NOR
B0)
Application: Comparators are used in central processing unit s (CPUs) and
microcontrollers (MCUs). Examples of digital comparator include the CMOS
4063 and 4585 and the TTL 7485 and 74682-'89.
Truth Table:
VHDL Code :
Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity S5 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
eq : out STD_LOGIC;
ag : out STD_LOGIC;
bg : out STD_LOGIC);
end S5;
architecture Behavioral of S5 is
begin
eq<='1' when a=b else '0';
ag<='1' when a>b else '0';
bg<='1' when a<b else '0';
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL codes of 4- bit Comparator is simulated &verified
EXPERIMENT NO. 6
AIM: Write a VHDL program to implement Up Counter
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
Counters are sequential logic devices that follow a predetermined sequence of
counting states which are triggered by an external clock (CLK) signal. The
number of states or counting sequences through which a particular counter
advances before returning once again back to its original first state is called the
modulus (MOD). In other words, the modulus (or just modulo) is the number
of states the counter counts and is the dividing number of the counter. The
decade counter has four outputs producing a 4-bit binary number, it receives an
input clock pulse, one by one, and counts up from 0 to 9 repeatedly.
Application: It suitable for human interfacing where a digital display is
required.
VHDL Code :
Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UpCounter is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (3 downto 0));
end UpCounter;
architecture Behavioral of UpCounter is
signal count : std_logic_vector(0 to 3);
begin
process(rst,clk)
begin
if (rst = '1') then count <= "0000";
elsif (clk'event and clk = '1') then count <= count+1;
end if;
end process;
o <= count;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL codes of Mod-10 up counter is simulated &verified.
EXPERIMENT NO. 7
AIM: Write a VHDL Program to generate the 1010 sequence detector. The overlapping
patterns are allowed
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
The objective of this experiment is to introduce the use of sequential logic. The
sequence is a sequential circuit. In sequential logic the output depends on the
current input values and also the previous inputs. When describing the
behavior of a sequential logic circuit we talk about the state of the circuit. The
state of a sequential circuit is a result of all previous inputs and determines the
circuit’s output and future behavior. This is why sequential circuits are often
referred to as state machines. Most sequential circuits (including our sequence
detector) use a clock signal to control when the circuit changes states. The
inputs of the circuit along with the circuit’s current state provide the
information to determine the circuit’s next state. The clock signal then controls
the passing of this information to the state memory. The output depends only
on the circuit’s state, this is known as a Moore Machine. Figure 7.1 shows the
schematic of a Moore Machine.
Fig: Schematic of a clocked synchronous state machine (Moore Machine)
A sequence detector is a digital circuit or algorithm designed to identify the presence or
absence of a specific sequence of binary bits in a stream of input data. It is commonly used
in digital signal processing, communication systems, and control systems. The sequence
detector monitors the input stream and produces an output when the specified sequence is
detected. There are two primary types of sequence detectors: synchronous and
asynchronous.
Synchronous Sequence Detector:
In a synchronous sequence detector, the detection process is synchronized with a clock
signal. The input stream is sampled at specific clock intervals, and the detection logic
operates based on these clocked samples. The most common type of synchronous sequence
detector is the Finite State Machine (FSM), which uses a set of states and transitions to
recognize sequences.
Asynchronous Sequence Detector:
An asynchronous sequence detector, on the other hand, doesn't rely on a clock signal for
sampling. It continuously monitors the input and triggers the detection logic whenever the
specified sequence is identified. Asynchronous detectors are often simpler than
synchronous ones but may be more susceptible to noise and timing variations.
A sequential circuit’s behavior can be shown in a state diagram. The state diagram for our
sequence detector is shown in figure 7.2. Each circle represents a state and the arrows show
the transitions to the next state. Inside each circle are the state name and the value of the
output. Along each arrow is the input value that corresponds to that transition.
A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to
1 when a target sequence has been detected. There are two basic types: overlap and
non-overlap. In a sequence detector that allows overlap, the final bits of one
sequence can be the start of another sequence. Example: 11011 detector with
overlap X 11011011011 Z 00001001001 11011 detector with no overlap Z
00001000001
Applications:
In a computer network like Ethernet, digital data is sent one bit at a time, at a very
high rate. Such a movement of data is commonly called a bit stream. One
characteristic is unfortunate, particularly that any one bit in a bit stream looks
identical to many other bits. Clearly it is important that a receiver can identify
important features in a bit stream. As an example, it is important to identify the
beginning and ending of a message. This is the job of special bit sequences called
flags. A flag is simply a bit sequence that serves as a marker in the bit stream. To
detect a flag in a bit stream a sequence detector is used.
VHDL Code :
Behavioral Modelling\
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SeqDetector is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end SeqDetector;
architecture Behavioral of SeqDetector is
type state_type is (s0,s1,s2,s3);
signal state:state_type:=s0;
begin
process(clk, reset)
begin
if( reset = '1' ) then
output <= '0';
state <= s0;
elsif ( clk' event and clk='1' ) then
case state is
when s0 => --when the current state is s0
output <= '0';
if ( input = '0' ) then
state <= s0;
else
state <= s1;
end if;
when s1 => --when the current state is s1
if ( input = '0' ) then
state <= s2;
output<='0';
else
state <= s1;
output<='0';
end if;
when s2 => --when the current state is s2
if ( input = '0' ) then
state <= s0;
output<='0';
else
state <= s3;
output<='0';
end if;
when s3 => --when the current state is s3
output<='1';
if ( input = '0' ) then
state <= s1;
else
state <= s2;
output <= '1'; --Output is 1 when the
--pattern "1010" is found in the sequence.
end if;
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: Thus, the VHDL code for the 1010 sequence detector circuit was simulated and
verified.
EXPERIMENT NO. 8
AIM: Write a VHDL code to implement serial to parallel of 4 bit binary number
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
The operation is as follows. Let’s assume that all the flip-flops ( FFA to FFD )
have just been RESET ( CLEAR input ) and that all the outputs QA to QD are
at logic level “0” ie, no parallel data output. If a logic “1” is connected to the
DATA input pin of FFA then on the first clock pulse the output of FFA and
therefore the resulting QA will be set HIGH to logic “1” with all the other
outputs still remaining LOW at logic “0”. Assume now that the DATA input
pin of FFA has returned LOW again to logic “0” giving us one data pulse or 0-
1-0. The second clock pulse will change the output of FFA to logic “0” and the
output of FFB and QB HIGH to logic “1” as its input D has the logic “1” level
on it from QA. The logic “1” has now moved or been “shifted” one place along
the register to the right as it is now at QA. When the third clock pulse arrives
this logic “1” value moves to the output of FFC ( QC ) and so on until the
arrival of the fifth clock pulse which sets all the outputs QA to QD back again
to logic level “0” because the input to FFA has remained constant at logic level
“0”. The effect of each clock pulse is to shift the data contents of each stage
one place to the right, and this is shown in the following table until the
complete data value of 0-0-0-1is stored in the register. This data value can now
be read directly from the outputs of QAto QD. Then the data has been
converted from a serial data input signal to a parallel data output. The truth
table and following waveforms show the propagation of the logic “1” through
the register from left to right as follows.
Fig: 4-Bit Serial In to Parallel Out Shift Register
Fig: Basic Data Movement through a Shift Register
VHDL Code :
Behavioral Modelling\
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity S2P is
Port ( x : in STD_LOGIC;
y : inout STD_LOGIC_VECTOR (3 downto 0);
clr : in STD_LOGIC;
clk : in STD_LOGIC);
end S2P;
architecture Behavioral of S2P is
begin
process(clk)
begin
if(clr='1')then
y<="0000";
elsif(clk'event and clk='1')then
y(3)<=x;
y(2)<=y(3);
y(1)<=y(2);
y(0)<=y(1);
end if;
end process;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL code to implement serial to parallel of 4 bit binary number is
simulated and verified.
EXPERIMENT NO. 9
AIM: Write a VHDL program to perform parallel to serial transfer of 4 bit binary
number
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
Parallel-in/ serial-out shift registers do everything that the previous serial-in/
serial-out shift registers do plus input data to all stages simultaneously. The
parallel-in/ serial-out shift register stores data, shifts it on a clock by clock
basis, and delays it by the number of stages times the clock period. In addition,
parallel-in/ serial-out really means that we can load data in parallel into all
stages before any shifting ever begins. This is a way to convert data from a
parallel format to a serial format. By parallel format we mean that the data bits
are present simultaneously on individual wires, one for each data bit as shown
below. By serial format we mean that the data bits are presented sequentially in
time on a single wire or circuit as in the case of the “data out” on the block
diagram below.
Fig: Parallel-In Serial-Out Shift Registers with 4 Stages
Applications:
1.Bit serial operations can be performed quickly through device iteration
2. Iteration (a purely combinational approach) is expensive (in terms of # of
transistors, chip area, power, etc).
3. A sequential approach allows the reuse of combinational functional units
throughout the multi-cycle operation
VHDL Code :
Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity P2S is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (3 downto 0);
dout : out STD_LOGIC);
end P2S;
architecture Behavioral of P2S is
begin
piso : process (clk,reset,load,din) is
variable temp : std_logic_vector (din'range);
begin
if (reset='1') then
temp := (others=>'0');
elsif (load='1') then
temp := din ;
elsif (rising_edge (clk)) then
dout <= temp(3);
temp := temp(2 downto 0) & '0';
end if;
end process piso;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: VHDL program to perform parallel to serial transfer of 4 bit binary number is
simulated and verified.
EXPERIMENT NO. 10
AIM: Write a program to design a 2 bit ALU containing 4 arithmetic & 4 logic
operations
APPRATUS:
Hardware Requirement: Computer
Software Requirement: ISE 14 Software
THEORY:
An ALU stands for arithmetic logic unit ALU is a digital circuit used to
perform arithmetic and logic operations. It represents the fundamental building
block of the central processing unit of CPU. Modern CPUs contains very
powerful and complex ALUs. In some processors ALU is divided into two
units an arithmetic unit and a logic unit.
Applications:
1. Data Processing: The ALU is at the core of data processing in computers,
handling numerical calculations and logical operations necessary for executing
programs.
2. Cryptography: ALUs are used in cryptographic algorithms to perform complex
mathematical operations required for secure communication, encryption, and
decryption.
3. Graphics Processing: In graphics processing units (GPUs), specialized ALUs
handle parallel processing tasks related to rendering and manipulating graphical
images and video.
4. Scientific Computing: ALUs are crucial in scientific simulations and
calculations, where intricate mathematical operations are required for
modeling physical phenomena, conducting simulations, and analyzing
data
VHDL Code :
Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( inputA : in STD_LOGIC_VECTOR (3 downto 0);
inputB : in STD_LOGIC_VECTOR (3 downto 0);
outputA : out STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
PROCESS(inputA,inputB,sel)
BEGIN
case sel is
when "000" => outputA<=inputA+inputB;
when "001" => outputA<=inputA-inputB;
when "010" => outputA<=inputA-1;
when "011" => outputA<=inputA+1;
when "100" => outputA<=inputA and inputB;
when "101" => outputA<=inputA or inputB;
when "110" => outputA<=not inputA;
when "111" => outputA<=inputA xor inputB;
when others => NULL;
end case;
END PROCESS;
end Behavioral;
OUTPUT & OBSERVATIONS:
RTL Schematic Diagram:
Behavioral Simulation Result (Time Period is 1 microsecond):
RESULT: Design of 2 bit ALU containing 4 arithmetic & 4 logic operations is
simulated and verified
