UNIT 8 TRANSISTORS

Structure
8.1 Introduction
Objectives
8.2 Bipolar Junction Transistors (BJT)
8.2.1 Transistor Action
8.2.2 Common Base(CB) Configuration
8.2.3 Characteristics of Transistor in CB Configuration
8.2.4 Common Emitter ( CE) Configuration
8.2.5 Common Collector Configuration (Emitter Followers)
8.2.6 Biasing of Transistors Load Line, Q-Point
8.2.7 Transistor as a Controlled Switch
8.2.8 Transistor as an Amplifier
8.3 Field Effect Transistor (FET)
8.3.1 Transistor Action
8.3.2 V-I Characteristics and Biasing
8.3.3 FET as a Controlled Switch
8.3.4 FET as an Amplifier
8.4 Differential Amplifier
8.5 CMOS Inverter
8.6 Summary
8.7 Answers to SAQs

8.1 INTRODUCTION
In Unit 7, you were introduced to the characteristics and applications of diodes.
In the present unit, you will learn about transistors, their classification, properties
and applications. Diodes and transistors are the most basic of discrete electronic
devices and are used in many electronic circuits. Even though modern electronics
largely employs integrated circuits (IC’s), the latter in fact are nothing but
assemblies of a large number of transistors and other circuit elements, all
fabricated in a single semiconductor chip. The transistor derives its name as a
short form of transfer resistor, which describes its action of transferring a signal
current from a low resistance input circuit to a high resistance output circuit in a
particular configuration.
Unlike a diode which is a two-terminal device, transistors are three terminal
devices with one terminal being the input terminal, a second one being the output
terminal and the third one being the common terminal for the input as well as the
output. The input pair of terminals may have an input voltage or current as the
controlling quantity and the output pair has its voltage or current controlled by the
input variable. If the input voltage controls the output current the parameter
associated with this linear relationship is termed the forward transfer
conductance, gm.
There are different types of transistors popularly available, one known as Bipolar
Junction Transistor (BJT) and the other known as Field Effect Transistor (FET).
The relationship between input voltage and output current in the case of BJT is
exponential. The relationship of input voltage and output current in the case of
FET is a square law. The devices of operated in the proper regions can act as
controlled switches or amplifiers. Both these applications will be highlighted in
this unit. You will also learn about differential amplifiers and inverters.
 Objectives
Basic Electronics – I
After studying of thus unit, you should be able to
 describe the input/output characteristics of the two types of transistors
viz., BJTs and FETs,
 describe how to bias these transistors to make them work in the
regions of interest,
 explain their use as controlled switches and amplifiers,
 identify these transistor amplifiers as controlled sources, and
 describe the working of a differential amplifier and a CMPS inverter.

8.2 BIPOLAR JUNCTION TRANSISTOR (BJT)

A bipolar transistor is a device with two p-n junctions as shown for example in
Figure 8.1(a). This is one of the possible types of BJT known as pnp transistor.
The other type is npn transistor. The symbol for a pnp transistor is shown in
Figure 8.1(b). Figure 8.1(c) is the symbol of an npn transistor.
8.2.1 Transistor Action
Consider the pnp transistor of Figure 8.1(a). One of the p regions is heavily doped
(p+). That region is called the emitter (E). The other p is called the collector (C).
The n region sandwitched between these two regions is known as base (B). This
region is made very thin.

IE IC
P+ N P
Emitter Collector
(E) (C)
_ _
+ VEB + VBC
IB
Base (B)

(a) The pnp Transistor

C

E C B

(b) Symbol for a pnp Transistor (c) Symbol for an npn Transistor
Figure 8.1

When the EB junction (emitter-base junction) is forward biased, a large number of

holes which are the majority carriers in the emitter region get injected into the
base region and a small number of electrons from n region get injected into the
emitter region constituting the total emitter current IE. In order to get good
transistor action, the major portion of IE should be made up of hole current. This
is achieved by making the emitter region more heavily doped than the base region.
This is said to increase the emitter efficiency. After the holes get injected into the
base, the holes tend to recombine with electrons in the base. This loss of holes
arriving at the BC junction to those injected is termed the base transport factor. It
44
must be kept close to one. The BC junction is reverse biased so that the field in
the BC depletion region easily collects the holes arriving at the junction. Thus, Transistors
almost the entire current at the emitter is available at the controller current, IC.
IC   I E , . . . (8.1)
where  is very close to 1. This is what is termed as bipolar transistor action.
Restating the same, when the emitter base junction of a BJT is forward biased and
the collector base junction, when the emitter base junction of a BJT is forward
biased and the collector base junction is reverse biased the collector current is
very nearly the same as the emitter current. This is valid for VBC  0, i.e. as long
as CB junction is reverse biased for a pnp transistor.
Since I E  I B  IC , . . . (8.2)
I B  I E  IC

 I E (1  )

But IC   I E

IC 
Therefore,   . . . (8.3)
IB 1  

The action in an npn transistor is similar, except that now all voltage polarities
and current directions are reversed.

Example 8.1

(a) Let  = 0.99 for a BJT. Determine .

(b) For the same transistor if the emitter current is 1 MA, determine the
base and collector currents.
Solution
0.99
(a)   99
1  0.99

This indicates a typical value of .

(b) I E  1 mA

Therefore, I C  0.99 mA

and I B  (1  0.99) mA  0.01 mA or 10 A.

8.2.2 Common Base Configuration

The common base configuration for n-p-n and p-n-p transistor is shown in
Figure 8.2.
As the name suggest in this configuration base terminal is made common to both
input and output. Input is applied between base and emitter and output is taken
across base and collector.

45
Basic Electronics – I

RE RC RE RC
1 2 1 2
N N N
IE P IC
IE IC

VEE IB VEE IB
VCC
VCC
3 3 3 3

(a) CB Configuration for NPN Transistor (b) CB Configuration for PNP Transistor
Figure 8.2
In this configuration input voltage is VEB and input current is Ic.
For CB Configuration
IC = dc IE + Ico . . . (8.4)
Where dc = Current amplification factor for CB configure
As Ico is very small
 Ic  dc IE . . . (8.5)
From Eq. (5.4)
IE = IC + IB . . . (8.6)
Substituting value of IC obtained in Eq. (8.1) in above equation we get,
IE = IB + (dc IE + ICO)
 IB = IE (1 – dc) + ICO
Neglecting ICO, we get
IB = IE (1 – dc) . . . (8.7)
2.2.3 Characteristics of Transistor in CB Configuration Input
Characteristics
For any configuration of transistor input characteristics are plotted between input
current and voltage keeping output voltage constant.
In CB configuration input characteristics are plotted between IE and VEB keeping
VCB constant. The characteristics are as shown in Figure 8.3.
As seen from the Figure 8.3 the input characteristics of a transistor are exactly similar
to that of forward biased diode. Uptill the cut in voltage the diode between base and
emitter is reverse biased so very little current flows. Once the diode is forward biased
heavy current flows, the current increases rapidly for a small change in the input
voltage.
VCB = 5V
VCB = 10V VCB = 0V
IE
(mA)

VEB (V)

Figure 8.3 : Input Characteristics

46
 Transistors
Output Characteristics
For any configuration of transistor output characteristics are plotted between
output current and output voltage keeping input current constant.
For CB configuration output characteristics are plotted between IC and VCB
keeping IE constant. The nature of graph is as shown in Figure 8.4.

IC
(mA) Active Region Break Down

Saturation IE = 5mA
Region IE = 4mA
dIE = 3mA
IE = 2mA

IE = 1mA

Cut-Off Region

Figure 8.4 : Output Characteristics

The output characteristics are divided into three regions of operation
Cut off Region
It is the region where both the junctions are reverse biased and so only the
reverse leakage current is flowing thus this region is below the graph having
IE = 0, and transistor is said to be in off state.
Saturation Region
It is the region where both the junctions are forward biased, and therefore in
saturation region VCB values are negative. The Collector current Ic increases
exponentially with increase in VCB value towards zero.
Acting Region
In this region, the collector current IC is almost equal to IE. Therefore if IE is
constant IC also remains constant irrespective of change in VCB. Because of
this nature in active region, the transistor in CB configuration works as an
constant current source.
Breakdown
When VCB voltage is increased beyond certain limit. As it is the reverse bias
voltage, the width of depletion region at collector junction starts to increase
at a particular value of reverse bias applied the depletion regions at emitter
and collector junctions are joined together and heavy current flows through
the transistor, and it is said that transistor has gone into breakdown
condition. This phenomenon is known as punch through or reach through
effect. This effect may permanently damage the transistor.
8.2.4 CE Configuration
The common emitter configuration for n-p-n and p-n-p transistor is shown in
Figure 8.5.
In this configuration input voltage and current are VBE and IB respectively where

47
 as output voltage and current are VCE and IC respectively
Basic Electronics – I
IC
IC

RC

+ RB -
RB -
+
VCC
IB IB
VCC
VCE VBE
VBB IE VBB
VBE
VCE
IE
- -
+ +
+

Figure 8.5
For CE configuration
We know that
IE = IC + IB . . . (8.8)
where IC = dc IE + ICBO
Rearranging above equation;
IC – ICBO = dc IE
Dividing both sides by dc
IC ICBO
   IE . . . (8.9)
dc dc
From Eqs. (8.8) and (8.9)
IC I  1  I
 I C  I B  CBO  Ic   1  I B  CBO
 dc  dc   dc   dc

1   dc  I CBO
 IC    IB 
  dc   dc

   I
 I C  I B  dc   CBO . . . (8.10)
1   dc  1   dc
  
Let dc   dc  . . . (8.11)
1   dc 
ICBO
 IC  dc I B  . . . (8.12)
(1  dc )
dc
As dc 
1  dc
 dc
1  dc  1
1  dc
1
1  dc  . . . (8.13)
1   dc

48
Substituting above value in Eq. (8.13)
Transistors
IC = dc IB + (1 + dc) ICBO . . . (8.14)
Reverse leakage current in CE configuration is given by
ICEO = (1 + dc) ICBO . . . (8.15)
 IC = dc IB + ICEO
Since ICEO is very small, so neglecting it
IC = dc IB . . . (8.16)
IC
or dc  . . . (8.17)
IB

As dc is ratio of output and input current it is called common emitter current
gain.
Relation between dc and  dc
dc
We know that dc 
1  dc

Dividing both sided by 1+dc we get,

 dc
dc 1   dc

1  dc 1  dc

 dc
dc 1   dc  dc
     dc
1  dc    1   dc   dc
1   dc 
 1   dc 
dc
 dc  . . . (8.18)
1  dc
Characteristics in CE Configuration
Input Characteristics
The input characteristics are plotted between IB and VBE keeping VCE
constant. As seen from the Figure 8.6 input characteristics are exactly
similar to that of CB configuration.

IB VCE = 0V 5V 10V
(µ A)

VEB (V)

Figure 8.6 : Input Characteristics in CE Configuration

49
 Output Characteristics
Basic Electronics – I
Figure 8.7 shows the output characteristics of transistor in CE configuration.
Active Region
IC
(mA) IB = 40
µA
Saturation IB = 30
Region µA
IB = 20
µA
IB = 10
µA IB = 0 µA

Cut-off Region VEB (V)

Figure 8.7 : Output Characteristics in CE Configuration

The output characteristics are plotted between IC and VCE keeping IB
constant.
Various regions in the output characteristics are explained below
Cur off Region
As both emitter and collector junctions are reverse biased, this means IB = 0.
There exist a leakage current that flows around the junction and through the
surface of the material. This leakage current is proportional to VCB.
Saturation Region
In this both junction that is emitter and collector are forward biased. The
region extends from zero towards LHS.
Active Region
In this region “Transfer Region” action takes place and emitter junction is
forward biased and collector junction is reverse biased.
Active region is that portion that has the greatest linearity, that means the
region in which the curves for IB are nearly straight and equally spaced.
Active region is used for voltage, current, or power amplification.
8.2.5 Common Collector Configuration (Emitter Follower)
The common collector (CC) configuration for n-p-n and p-n-p transistors is as
shown in the Figures 8.8 (a) and (b).
IE IE

IB IB

VCC
VCC
IC
IC
VBB VBB

(a) N-P-N Transistor (b) P-N-P Transistor

Figure 8.8

50
In this input voltage is VBC and input current is IE where output voltage is VEC and
output current is IC. This configuration is also known as emitter follower. Transistors

It is primarily used for impedance matching purpose, as it has high input

impedance and low output impedance as compared to CB and CE configurations.
Input Characteristics
It is an plot of input voltage VBC verses IB keeping VEC constants, as shown
in Figure 8.9.

IB VEC = 1V VEC = 2V
( A)

1.5 V 2.5 V
VBC (V)

Figure 8.9 : Input Characteristics for CC Configurations

Assume VEC to be 1 V, the base emitter junction is not forward biased upto
VBC =1.5 V. Then it increases rapidly as the VBC is increased beyond 1.5 V.
This is because B-E junctions is more and more forward biased.
Output Characteristics
It is a graph between output current IE versus output voltage VEC keeping IB
constant.

IB = 60  A

IB = 40  A

IB = 20  A
IB =  A

VBC (V)

Figure 8.10 : Output Characteristics for CC Configuration

IT is clear from Figure 8.10, output characteristics of CC configuration are
exactly similar to that output characteristics in CE configuration. This is
because IC  IE.
Current Relation in CC Configuration
We know that IE = IC + IB
Substituting IC as IC = dc IE + ICBO
IE = dc IE + ICBO + IB . . . (8.19)
IB ICBO
 IE   . . . (8.20)
(1  dc ) (1  CBO )

51
 1
Basic Electronics – I Also as (1  dc ) 
1   dc
 IE = (1 + dc) IB + (1 + dc) ICBO . . . (8.21)
Neglecting ICBO
 IE = (1 + dc) IB . . . (8.22)
IE
or Current gain   1  dc . . . (8.23)
IB
Sl. No. Parameter CB CE CC
1. Common Terminal Base Emitter Collector
2. Current Gain IC IC IE
dc  dc   (1  dc )
IE IB IB
3. Voltage gain Medium Medium Unity
4. Input Resistance Very low Low High
(21.68) (1k) (500k)
5. Output Resistance Very high High Low
(1m) (40k) (50)
6. Application AS per Audio For impedance
amplifier Amplifier
matching
7. Input Current IE IB IB
8. Output current IC IC IE
9. Input Voltage VEB VBE VBC
10. Output voltage VCB VCE VEC

8.2.6 Biasing of Transistors, Load Line, Q Point

Transistors while being amplifiers are working in active region and need to be
biased emitter base in forward direction and collector base in reverse direction.
The biasing is done to operate the device in the linear region and Q point need to
be established, i.e. point of operation under quiescent condition, i.e. no input
signal impressed on the transistor. Most transistor are operated in CE
configuration as shown in Figure 8.11. The input current and output voltage are
taken independent variables but input voltage and output current are taken as
dependant variables.
or VBE = f (VCE, IB) . . . (8.24)
IC = f (VCE . IB) . . . (8.25)
The Eqs. (8.24) and (8.25) represent families of curves. For a given IB, IC is not
much dependent on VCE, The relation has been plotted as output characteristics in
Figure 8.12.
IC

RL
IB VC
E
VB
E +
VC
C

Figure 8.11 : Transistor in CE Configurations

52
 IB = 125  A Transistors
VCC
RL
50 100  A
40
Q 75  A Ibo
30 Pm = VCIC

IC (m A)
50
ICC 20 A
25  A Load Line (d.e)
10 Slope = - 1/RL
R
0 2 4 6 8 10 V
VCEO VCE VCC

Figure 8.12 : Load Line and Q Point

The equation for collector emitter loop can be expressed as
VCE = VCC – IC RL . . . (8.26)
VCE VCC
or IC    . . . (8.27)
RL RL
1
The Eq. (6.10) desiquated a straight line with slope   and interception IC
RL
Vcc
axis at and intercept VCE axis as VCC represented by st. line PQR is called the
RL
dc load line. If the transistor is biased for Ic = Ibon then the point Q of intersection
of PR with characteristic corresponding to no signal impressed at the input. The
point of operation should be below Pmax hyperbole so that power dissipation of
the transistor does not exceed the permissible dissipation Pm.
Biasing Method
In active region the emitter junction is forward biased and collector junction
is reverse biased. It is not necessary to use two different dc sources for this
purpose. In fact both the biasing can be derived from the same source to
economicse battery. The schemes are as below.
Fixed Bias Circuit
Is shown in Figure 8.13.

IC RL
RB
+
A.C. VCC
A.C. Out Put -
IB
Input

Figure 8.13 : Fixed Bias Scheme

For base emitter loop the KVL equation, give
Vcc  VBE Vcc
IB   . . . (8.28)
RB RB
VBE is few tenths of volts across forward bias EB junction is small composes
with VCE hence IB is almost fixed.
The CB junction is reverse biased as n-collector of npn-transistor is
collected to positive terminal of the battery and
Ic =  IB . . . (8.29)
53
 and B is not dependant on collector load RL.
Basic Electronics – I
and VCE = VCC – IC RC . . . (8.30)
Biasing Scheme with Emitter Resistor is shown in Figure 8.14 and
Provides better bias stabilization to be discussed later section.
Writing KVL equation for box emitty side
VCC – IB RB – VBE – IE RE = 0 . . . (8.31)
+ VCC

RB IB RC IC
AC
Output
VCE
+ VBE
CE RE
VE
IE

Figure 8.14 : Biasing Scheme with emitter Resistor

One can also write
IE = IC + IB (by KCL)
= ( + 1) IB
Eq. (6.14) is transformed to
VCC – IB RB – VBE – IE RE = 0 . . . (8.32)
Vcc  VBE
Giving Is  . . . (8.33)
RB  (  1) RE
The KVL equation on collector side gives
VCC – IC RL – VCE – IE RE = 0
As B >> 1 IC  IE
 VE  IC RE
and VCE = VCC – IC (RL + RE) . . . (8.34)
The load line will have its slope modified due to RE and new slope is
1
 . . . (8.35)
RL  RE
A large capacitor CE is connected across RE as by pass capacitor to keep RE
short circuited from ac pointed of view.
DC Bias Circuit Independent of 
For the biasing schemes where Q point remains independent of  of a
transistor is shown in Figure 8.15 and popular scheme
The base to ground dc voltage VB can be expressed is
RB1
VB  . . . (8.36)
RB1  RB 2
and VE = VB – VBE . . . (8.37)

54
 VE
IL  . . . (8.38) Transistors
RE

+ VCC

IC RL
I1 RB1

A.C
Output
VCE
A.C
Input
I2 IE
RE VE

Figure 8.15 : Biasing Scheme Independent of B

As IC  IE
RB1
VB  . . . (8.39)
RB1  RB 2
VCE = VCC – IC RL – IE RE . . . (8.40)
and  does not affect any of relation 2.34 to 2.37. RL determined IL, RL
determines VCE, VB can be adjusted by RB2 and varying of  or replacement
of one transistor with other of same. No. does not affect operating point.
Biasing Stabilization
In any amplifier the operating point may change due to temperature
variation of the transistor due to following caused.
(a) The reverse saturation current ICO for collector base junction
charges due to change in temperature, for silicon devices it
doubles for every 10oC rise in temperature is in Eq. (6.5).
(b) Base emitter voltage will decrease at the rate of 2.5 mv/c for
silicon devices.
(c) The current gain B increases with temperature.
The shifting of bias point due to above reasons may cause distortion in
amplifiers. A good biasing scheme will no permit the Q point to shift due to
above reasons.
In general the collector current IC is function of ICO, VBE and  which change
with temperature one can express.
IC = f [ICO, VBE, ] . . . (8.41)
I C I C I
or I C  I CO  VBE  C B
I CO VBE B
Where IC is change in IC due to changes in ICO, VBE and B.
IC
We define S I   Current stabilisation factor .
ICO

55
 IC
Basic Electronics – I SV   Voltage stabilisation factor
VBE
IC
SB   Gain stabilisation factor
B
8.2.7 Transistor as a Controlled Switch
Figure 8.16(a) shows an npn transistor with emitter terminal as a common
terminal between input and output. Base is taken as the input terminal and
collector is taken as the output terminal. The reverse bias voltage is applied to the
output through RC connected in series with a bias supply voltage, VCC.
vi  v BE , iE  I EO [exp (VBE / VT )] . . . (8.42)
v0  vCE , iC   iE . . . (8.43)
Therefore, v0  vCC  iC RC
 vCC   I EO [exp (VBE / VT )] RC . . . (8.44)
(In electronic circuit diagrams, the dc power supplies are often omitted for the
sake of clarity. In Figure 8.16 (a), even if the dotted portion is omitted, it should
be taken that a voltage source of VCC volts is connected between the terminal
marked VCC and the ground. Also all node voltages wherever specified are to be
taken as referenced to ground.)

VO
C +
i
C
B
+ i + i
B E
Vi
- E -
-

Figure 8.16 (a) : Transistor Inverter/Switch

v0  vCC   I EO RC [exp (vi / VT )] . . . (8.45)
Figure 8.16(b) shows the output versus input characteristics of the transistor
switch/inverter of Figure 8.16(a).

Vcc

Cut off
I
VO II III

Vr
Saturation
Active

Vr Vi

Figure 8.16 (b) : Inverter Characteristics

Region I
v0  VCC because iC  0. Transistor has not yet started conducting. Only
when vi (vBE) reaches Vr called cut-in voltage ( 0.6 V for silicon), does a
substantial amount of current start flowing through RC. Till that point the
transistor is off.

56
Region II
Transistors
VBE  vi  Vr , BE junction is sufficiently forward biased, BC junction is
reverse biased. Therefore transistor action takes place and the transistor is
said to be in the active region. Eq. (8.45) depicts the output versus input
relationship or transfer function. Transistor amplifiers are operated in the
active region.
Region III
As vi increases v0 keeps decreasing. A point is reached when v0  VCE  VBE
making VCB  0 . After this point the CB junction starts getting forward
biased. Transistor action stops. Both junctions are forward biased and the
transistor is in the saturation region.

Example 8.2

(a) For an inverter circuit with VCC = 5 V and RC = 1 k , sketch v0 vs vi

assuming that a silicon transistor is being used. Assume
VT = 26 mV,  = 0.99 and a typical value of IEO, say 10 mA.
(b) For the transistor inverter shown in Figure 8.18(a) sketch v0 vs vi. For
input voltage levels Vi1 = 5 V and Vi2 = 0 V and VT = 26 mV,
determine the output voltage for a typical value of IEO for the
transistor is 0.99.
5V

1K

1K
V1
+

-

Figure 8.17 : Transistor Inverter of Example 8.2 (b)

Solution
5

VO
In 3
Volts
2

0
0 1 2 3 4 5
Vi In Volts
(a)

Figure 8.18 (a) : For Solution to Example 8.2 (a)

57
 5
Basic Electronics – I
4

VO
In 3
Volts
2

0
0 1 2 3 4 5
Vi In Volts

(b)
Figure 8.18 (b) : v0 vs vi of inverter of Figure 8.17

Vi 0V 5V
V0 5V 0V

If 0 V is represented as ‘0’ logic level and if 5 V is represented as ‘1’

logic level then we have,
Vi 0 1
V0 1 0

That is, if Vi  A then V0  A in logic notation, which you will learn

later. The symbol for transistor inverter which is one of the important
building blocks of digital circuits is shown in Figure 8.18(a).
The above analysis depicts the application of a transistor as an
electronic switch. The voltage on a load connected between the
collector C and the ground can be switched on or off by switching off
or on a control voltage at the input (between the base B and ground).
The point to note is that very little current and hence power is needed
from the source of the control voltage (as the base current is
negligibly small) while appreciable amounts of current/power can be
switched into or off from the load.
8.2.8 Transistor as an Amplifier
An amplifier is an electronic circuit which furnishes an output signal (voltage or
current) that is a faithful replica of the input signal (voltage or current). Ideally an
amplifier draws zero power from the source of the input signal, all the power
associated with the output signal being drawn the d. c. power supply energizing the
amplifier. In this respect, an amplifier differs from the ideal transformer and in
which all the output power comes from the source of input signal. Depending on
the nature of the input and output signals an ideal amplifier can be modeled in term
one of the four controlled sources.
In the active region of operation of a transistor, the transistor can be used as an
amplifier. Whereas in the transistor inverter case the transistor remains either
‘OFF’ or ‘ON’ and only transits from ‘ON’ to ‘OFF’ or ‘OFF” to ‘ON’, a
transistor amplifier must be biased so that when the signal to be amplified
appears, the transistor remains in the active region. The transistor biased to
receive the signal is said to be in quiescent condition. (A circuit is said to be in the
quiescent (resting) condition when it is not excited by an input signal). The

58
collector current and the CB reverse bias voltage known as the operating point of
the transistor give an idea of the signal handling capability of the transistor Transistors
amplifier.
Considering the circuit of Figure 8.16(a) again, if quiescent condition is fixed by a
voltage VBEQ then IEQ = IEO exp (VBEQ / VT).
VBEQ
I CQ   I EO exp
VT

VOQ  VCC  I CQ RC  VCC   RC I EO exp (VBEQ / VT ) . . . (8.46)

B
+
+
Bi

VBE

VBEQ

Figure 8.19 : Input Signal  vi Applied to the Amplifier

Suffix Q indicates quiescent conditions before the signal is applied.
When the signal is superimposed over the quiescent conditions with signal as a
change  vi as shown in Figure 8.19.
VBE  VBE  VBEQ

 Vi  VBEQ

iE  I EO exp [( vi  VBEQ ) / VT ]

 I EO exp (VBEQ / VT ) exp ( vi / VT )

 I EQ exp ( vi / VT )

iC   iE   I EQ exp ( vi / VT )  I CO exp ( vi / VT ) . . . (8.47)

Now v0  VCC  iC RC  VCC  RC I CQ exp ( vi / VT )

 v ( vi ) 2 
v0  VOQ   v0  VCC  I CQ RC 1  i  . . .
 VT 2VT 2 
 
But VOQ  VCC  I CQ RC

 I CQ RC   vi 
Therefore,  v0   vi 1   . . . . . . (8.48)
VT  2VT 
The relationship between  v0 and  vi can be assumed to be linear only if
 vi / 2VT  1 or  vi  2VT  52 mV at room temperature.

In this situation, termed small signal operation,  v0 /  vi is called the voltage

gain Av of the amplifier and it is given by – (ICQ / VT) RC when operating around
the operating point ICQ. The negative sing indicates inversion of phase reversal.
The circuit is known as common emitter amplifier. ICQ / VT is a small signal
parameter relating change in output current with change in input voltage linearly
and is called the transconductance gm of the transistor at its operating point.

59
Basic Electronics – I Example 8.3

(a) Determine the voltage gain of a common emitter amplifier having RC as

1 k and operating at 1 mA collector current.
(b) Evaluate the input resistance Ri seen by the source supplying voltage
change  vi in Example 8.3(a).
Solution
 v0  I CQ RC
(a)  AV   g m RC 
 vi VT

 10 3  103
   38.5
26  10 3
(b) Ri = input resistance
change in input voltage

change in input current
 vi  vi  v0  vi  v0  v0
   
 ii  ii  ii  ii  i0  ii

1
 . RC . 
| AV |


  99  26   2.574 k
gm

SAQ 1

(a) The  of a BJT is given as 0.998. Determine its . If  changes by 1%

by how much does  change?
 IC
(b) For a BJT evaluate known as transconductance at any operating
VBE
point.
 IE
(c) For a BJT evaluate at any operating point.
VBE

(d) For a BJT operating at an emitter current of 1 mA, determine the

 IE
transconductance gm and .
VBE

8.3 FIELD EFFECT TRANSISTOR (FET)

There are two types of FETs, Junction FET (JFET) and Metal Oxide
Semiconductor FET (MOSFET). The basic characteristics however is the same
for both the types namely the output current and input voltage have a square law
relationship.

8.3.1 Transistor Action

60
JFET comprises a channel (n or p type) between source and drain whose width is
controlled by gate (p or n type) (vide Figures 8.20(a), (b) and (c)). In what Transistors
follows, we shall discuss the transistor action in relation to an n-channel FET.
Gate (G)

Source Drain
(S) (S)
n+ n+

P-
Substrate

(a) : An n-Channel JFET

D D

G G

S S

(b) Symbol for n-Channel JFET (c) Symbol for p-Channel JFET
Figure 8.20
The pn junction between channel and gate is having a depletion layer vide
Figure 8.21(a) whose width increases as the magnitude of the reverse bias voltage
increases. This control facilitates the dependence of current through the channel
on the reverse bias voltage appearing across the depletion layer. As the gate is
isolated from the channel by the reverse biased junction, almost no gate current
flows as the control action takes place. As the voltage VDS increases the current in
the channel (IDS) increases but the quantum of increase in current progressively
decreases for a quantum change in voltage VDS vide Figure 8.21(b). This is
because the depletion layer width increases as gate to drain voltage is increased
for a fixed gate to source voltage. At a point when the depletion layer width
almost covers the entire channel over the drain and the current increase quantum
becomes zero, the current reaches a saturation value. This condition is known as
‘pinch off’. In the general case, the gate G is kept at a negative potential with
respect to the source S for an n-channel JFET. The saturation current then depends
on VGS as shown in Figure 8.22.
VD IDS
S
Depletion
S G D Regions

n+ - n+
source n channel drain

p- substrate

(a) Formation of Depletion Layer in n-Channel JFET by Biasing

61
Basic Electronics – I Dynamic Resistance
Increases Nonlinearly
IDSS VGS = 0V
Current
Linear (Ohmic) Region
Region

VP (Pinch-off Voltage)

(b) IDS Vs VDS for VGS = o in an n-Channel JFET

Figure 8.21

8.3.2 V-I Characteristics and Biasing

 VGS  VDS
When VDS is small, I DS  2 I DSS 1   and after pitch off
 VP  |VP |
2
 V 
I DS  I DSS 1  GS  , where IDSS is known as the saturation current for
 VP 
VGS = 0 V and VP is known as the ‘pinch off’ voltage. It can be seen that IDS = 0
for VGS = VP when the entire channel is blocked the beginning itself.
FETs can be used as voltage variable resistors (VVR) when working in the region
where IDS is linearly related to VDS below ‘pinch off’. They can be used for
amplifier purposes when they are biased to operate in the current saturation region
beyond ‘pinch off’.

Example 8.4

(a) An n-channel JFET with characteristics shown in Figure 11.8 is to be

used as a VVR. Determine the channel resistance for VGS = 0. Write
down the expression for the voltage dependent resistance.
IDS (mA)

VGS =0
VGS = 1V
VGS = 2V
VGS = 3V
VGS = 4V
VDS (V)
5 10 15
VGS = 5V

Figure 8.22 : JFET Characteristics for Example 8.4(a)

(b) The JFET with characteristics shown in Figure 8.22 is to be used as an
amplifier. Determine its transconductance when VGS =  1 V.
Solution
(a) In the linear region,
 V  VDS
I DS  2 I DSS 1  GS  . . . (8.49)
 VP  |VP |
 I DS 2 I DSS
Therefore,  for VGS  0 . . . (8.50)
 VDS |VP |

Therefore, R  250 Ω for VGS  0

62
 For VGS  0,
Transistors
250
R Ω
  VGS 
1   
   5 
2
 V 
(b) I DS  I DSS 1  GS 
 VP 
 I DS 2 I DSS  V 
gm   1  GS  . . . (8.51)
 VGS  VP  VP 
2  10  10  3  1
 1   S
5  5
20  4
 mS  3.2 mS
55

Region beyond VDS  4 V is the region of current saturation for

VGS =  1 V.
Depletion MOSFET
The depletion type MOSFET has similar characteristics as JFET.
Construction-wise it is different from JFET and is illustrated in
Figure 8.23(a). There is an illustrated layer of SiO2 called gate oxide
between the channel and the gate contact. Therefore the gate can be
negatively so as to deplete the existing channel or positively to enhance the
channel width. However it is normally operated in the depletion mode.
G SiO2
S D

n n

Substrate

(a) Construction of n-channel MOSFET

D D

G G

S S

(b) Symbol for n-channel Depletion (c) Symbol for p-channel Depletion
Mode MOSFET Mode MOSFET
Figure 8.23

63
 Enhancement MOSFET
Basic Electronics – I
Consider Figure 8.24(a), which shows the construction on n-channel
enhancement MOSFET.
Here there is no n-channel diffused between the source and drain. In order
to create a channel the substrate to gate potential must be made positive.
G SiO2
S D

n n

Substrate

Figure 8.24(a) : Construction of Enhancement Type n-Channel MOSFET

The voltage to applied to the gate to create an n-channel on the surface is
called the threshold voltage, VT. After the channel is created by applying a
voltage greater than the threshold voltage, MOSFET action can be allowed
to occur. Mathematically, the equations and v-i characteristics are similar to
those of depletion mode MOSFET of JFET. But in the saturation region the
drain current is given by
I DS  K (VGS  VT ) 2 ,

where K is in mA / V2, VT is the threshold voltage and IDS is in mA. The

symbols for the n-channel and p-channel MOSFETS of this type are shown
in Figures 8.24(b) and (c).

(b) : Symbol for n-Channel (c) Symbol for p-Channel

Enhancement Type MOSFET Enhancement Type MOSFET
Figure 8.24

8.3.3 FET as a Controlled Switch

Amongst the different types of JFETs, the enhancement type of MOSFET is
ideally suited as a switch because it is normally off (i.e. with VGS = 0 V) and in
order to switch it on, a voltage greater than threshold voltage is to be applied to
the gate with respect to the source.
Figure 8.25(a) shows the basic MOS inverter circuit using p-channel enhancement
type MOSFET. Gate is the input terminal, source is the common terminal between
64
input and output and the drain is the output terminal. The supply voltage VDD is
applied through a resistor RD to the drain. Transistors

+VDD

RD

iD +
VD
+
Vi
- -

Figure 8.25(a) : MOSFET Inverter Switch

vi  vGS , v0  v DS

iD  K (vGS  VT ) 2 for vGS  VT

and v DS  vGS  VT . . . (8.52)
In the current saturation region.
Therefore, v0  VDD  iD RD

v0  VDD  K (vi  VT ) 2 RD . . . (8.53)

As vi increased from zero until vi > VT the FET is in the cut-off region and
therefore v0 remains at VDD. Therefore the FET enters current saturation region
and Eq. (8.53) describes the transfer characteristics. In the active region when
v0  vi  VT the circuit enters saturation region.

VDD
Cut Active Saturation
OFF
VO

VDS1 VO = V i -
VT

VT VGSI
Vi

Figure 8.25 (b) : Transfer Characteristics of MOS-Transistor Switch

In order to use the MOSFET as a switch the following conditions are to be
satisfied. vi  VT for the switch to be ‘OFF’; vi  0 is a convenient voltage
vi  VGS 1 (vide Figure 8.25(b)) for the switch to be ‘ON’ where v0  VDS 1  0 .

8.3.4 FET as an Amplifier

In the active region of operation the MOSFET can be used as an amplifier. The
transistor biasing should be such as to maintain it in the active region when the
signal is present, e.g. for the circuit of Figure 8.25(a), vi  VT and v0  vi  VT for
the MOSET to remain in active region. In this region if the quiescent condition is
fixed by a voltage VGSQ then
I DQ  K (VGSQ  VT ) 2

VDSQ  VDD  K (VGSQ  VT ) 2 RD ,

65
 Suffix Q indicating quiescent conditions before the signal is applied.
Basic Electronics – I
When the signal is superimposed over the quiescent conditions with signal change
as  vi

iD  K (VGSQ   vi  VT ) 2

v0  VDD  K (VGSQ   vi  VT ) 2 RD

 VDD  K (VGSQ  VT ) 2 RD  2 K (VGSQ  VT )  vi RD  K ( vi ) 2 RD

v0  VDSQ  2 K (VGSQ  VT ) 2 RD  vi  K RD ( vi ) 2 . . . (8.54)

 v 
v0  V0Q   v0  VDSQ  2 K RD  vi (VDSQ  VT )  i 
 2 
The relationship becomes linear viz.,
 v0   2 K RD (VDSQ  VT )  vi

only when  vi  2 (VGSQ  VT ).

 v0
Then   2 K RD (VGSQ  VT )
 vi
  g m RD ,
where g m  2 K (VGSQ  VT ) is known as the transconductance of the FET around
  ID 
the quiescent condition  g m  |VGSQ  .
 VGS 

Example 8.5

(a) For the MOS transistor inverter shown in Figure 8.25(a),

VDD = 10 V, RD = 1 k, K = 5 mA / V2 and VT = 2 V, sketch v0 as a
function of vi. For voltages vi1 = 0 and vi2 = 10 V obtain the output
voltages.
Solution
(a) 10 V

VO
5V

VO = vi - 2

0 5V 10 V
Vi

Figure 8.26 : v0 – vi Relation for Example 8.5(a)

v0  10  5 (vi  2) 2 in the current saturation region (2 < vi < 3.5).

Vi 0V 10 V A

V0 10 V 0V A

66
 Transistors

SAQ 2

(a) For the transistor amplifier shown in Figure 8.27(a), determine IC and
VCB for VCC = 10 V. Assume  = 0.99.

10 V

4k
1M

+
CC
+ VO
II CC
n

Figure 8.27(a) : For SAQ 2(a)

(b) For the amplifier circuit of SAQ 2(a), evaluate the small signal
 v0 v
voltage gain, and small signal input resistance, i . Assume
 vi  ii
an appropriate value of VT.

8.4 DIFFERENTIAL AMPLIFIER

The amplifiers studied in Sub-sections 8.2.8 and 8.3.4 can amplify only input
voltages which are referenced to ground i.e. voltages between a node and the
ground. They are therefore called single-ended input amplifiers. A differential
amplifier, as its name suggested, can amplify the difference between two input
voltages each of which may be referenced to ground. Therefore, it can amplify
input voltages between two nodes neither of which need be grounded. The
differential amplifier is a basic block of most of the present day Analog ICs and
some of the Digital ICs. This block any of the single transistor amplifiers
discusses so far both the biasing technique as well as dynamic performance
characteristics. Therefore, it is not any longer necessary for us to study the
different ways of biasing a single transistor BJT or FET. Further, the operational
amplifier (opamp) IC which has now become very popular in its applications has
this block as the primary unit. Since biasing either the differential amplifier or the
opamp involves just connecting dual supplies  Vs to is supply terminals, the
users do not have to any longer worry about proper biasing for optimized
performance of the amplifier device.

67
Basic Electronics – I
VCC

RC RC
+ -
VC1 VC2
VO
T1 T2
Vi1 + + Vi2

VBE1 - - VBE2

IO

- VCC

Figure 8.28(a) : BJT Differential Amplifier

8.5 CMOS INVERTER

Figure 8.29(a) shows a CMOS inverter which belongs to the most popular logic
family used in VLSI (Very Large Scale Integrated Circuits). It is also used in
analog ICs as an output stage.
VSS

S VSS VO = Vi - VT 
VO
D
A
iD1 B
VT  VO = Vi - VT 

- VSS + VT  VSS - VT  Vi

iD2 C VT 

S - VSS

- VSS

(a) CMOS Inverter (b) CMOS Inverter Characteristics

Figure 8.29
Using MOSFETs which are having identical characteristics,
iD  K (VGS  VT ) 2
in the region where vDS  VGS  VT and bounded by lines
v0  vi  |VT | and v0  vi  |VT | ,
the gain  v0 /  vi is infinite as depicted in Figure 8.29(b). The MOS inverter can
be used as a NOT gate when the circuit operates with one of the transistors off
i.e., when vi   VSS or when vi   VSS . The advantage of this operation is that
the current drawn from the bias source is always zero. Therefore, the CMOS logic
family has the lowest power dissipation possible amongst all logic families
available today.

68
As an amplifier stage when the MOSFET are in the current saturation region
(region BC) with a load resistance RL, the voltage generation can be shown to be – Transistors
gm RL as in the case of other transistor amplifier stages discussed so far.

8.6 SUMMARY
This unit introduced you to bipolar and field effect transistors, their actions and
characteristics, their operating modes as switches (controlled) as well as
amplifiers. If then explained how these basic devices can be configured as
differential amplifiers and inverters. It also brought out the fact that an
Operational Amplifier the use of which we shall study in greater detail in the next
two units is nothing but a sophisticated different amplifier.

8.7 ANSWERS TO SAQs

SAQ 1
0.998
(a)   499
1  0.998

 
 0.01,  
 1 

  (1  )  

 (1  ) 2

1

(1  ) 2

    
 . .
   

 1  
   .
1    
Percentage change in   500  1%
 500%

(b) I C   I E 0 [exp (VBE / VT )  1]

 IC  I E0
 exp (VBE / VT )
VBE VT

IC   I E0

VT

IC

VT

 IE I  V  I  I E0
(c)  E 0 exp  BE   E
VBE VT  VT  VT

IE

VT

69
 (d) I E  1 mA, VT  26 mV
Basic Electronics – I
 IC I  I E 10 3  0.998
Therefore, g m   C    38.4 mS
VBE VT VT 26  10 3

 IE I
 E  38.5 mS.
VBE VT

SAQ 2
10  0.6
(a) IB  A  9.4 A
106

IC   I B  I B  99  9.4 A
1 
 0.931 mA

VCB  10  I C  4000  0.6  10  3.724  0.6

 5.676 V

 v0  I CQ 0.931
(b)   g m RC  RC    4  103   143
 vi VT 26

 Voltage gain =  143

 vi V 26
 T   0.99  100  2765 
 ii I CQ 0.931

Input resistance = 2.767 k.

70