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MODULE -3
COMBINATIONAL CIRCUIT DESIGN & SIMULATION USING GATES
Digital Logic Families
The following are the most popular digital logic families
 TTL – Transistor Transistor Logic
 ECL – Emitter Coupled Logic
 MOS – Metal-Oxide Semiconductor
 CMOS – Complementary Metal-Oxide Semiconductor
Characteristics of Logic Families
1. Fan-in
2. Fan-out
3. Propagation delay
4. Noise margin
5. Power dissipation

Fan-in: refers to the number of inputs in a digital logic gate family.

Fan-out: specifies the no. of standard loads that the output of typical gate can drive without impairing its
normal operation

Propagation delay: is the average transition time for a signal to propagate from input to output.

Noise margin: is the maximum external noise voltage added to an input signal that does not cause an
undesirable change in the output.

Power dissipation: it is the power consumed by the gate that must be available from power supply.
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REVIEW OF COMBINATIONAL CIRCUIT DESIGN

Steps

 Set up a truth table which specifies the output(s) as a function of the input variables.

 Derive simplified algebraic expressions for the output functions using Karnaugh Maps, or Quine-
McCluskey method, or any other similar procedure.

 The resulting algebraic expressions are then manipulated into the proper form, depending on the
type of gates to be used in realizing the circuit.

 Minimum two-level AND-OR, or NAND-NAND circuits can be realized using the minimum sum-of-
products. Minimum two-level OR-AND, or NOR-NOR circuits can be realized using the minimum
product-of-sums.

DESIGN OF CIRCUITS WITH LIMITED GATE FAN-IN

• In practical logic design problems, the maximum number of inputs on each gate is limited.

• Depending on the type of gates used, this limit may be two, three, four, eight etc..

• If a two-level realization of a circuit requires more gate inputs than allowed, factoring the logic
expression to obtain a multi-level realization is necessary.

Example 1: Realize the following functions using only two-input NAND gates and inverters.

𝑓1 = Σ𝑚 (0,2,3,4,5)

𝑓2 = Σ𝑚 (0,2,3,4,7)

𝑓3 = Σ𝑚(1,2,6,7)

GATE DELAYS AND TIMING DIAGRAMS

• When the input to a logic gate is changed, the output will not change instantaneously.

• The gates take a finite time to react to a change in input.

• So that the change in the gate output is delayed with respect to the input change.

• If the change in output is delayed by time, ε, with respect to the input, we say that, the gate has
a propagation delay of ε.
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Figure shows possible input and output waveforms for an inverter

Timing diagram for a circuit with two gates

• Each gate has a propagation delay of 20 ns

• Gate inputs B and C are held at constant values 1 and 0.

• Input A is changed to 1 at t = 40 ns and then changed back to 0 at t = 100 ns.

• The output of gate G1 changes 20 ns after A changes, and the output of gate G2 changes 20 ns
after G1 changes.
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HAZARDS IN COMBINATIONAL LOGIC

Fig. Hazards

• If, in response to any single input change and for some combination of propagation delays, a
circuit output may momentarily go to 0 when it should remain a constant 1, we say that the circuit
has a static 1-hazard.

• Similarly, if the output may momentarily go to 1 when it should remain a 0, we say that the circuit
has a static 0-hazard.

• If, when the output is supposed to change from 0 to 1 (or 1 to 0), the output may change three or
more times, we say that the circuit has a dynamic hazard.

Static 0-hazard.

• If A = B = C = 0 and then output F =0.

• When B changes from 1 to 0 then output F should remain a constant 0. Now E will go to 1 before
D goes to 0, resulting in a momentary 1 (a glitch) appearing at the output F .

• So F momentarily goes to 1. This is called Static 0 Hazard.

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Static 1-hazard.

• If A = C = 1 and B=1 then output F =1.

• When B changes from 1 to 0 then output F should remain a constant 1. Now E will go to 0 before
D goes to 1, resulting in a momentary 0 (a glitch) appearing at the output F .

• So F momentarily goes to 0. This is called Static 1 Hazard.

Detection of Static 1 Hazard

Hazards can be detected using a Karnaugh map.

• Write down the sum-of-products expression for the circuit.

• Plot each term on the map and loop it.

• If any two adjacent 1’s are not covered by the same loop, a 1-hazard exists for the transition
between the two 1’s.

To Eliminate Static 1 Hazard

• If we add a loop to the map of above Figure and, then, add the corresponding gate to the circuit
(as shown in the following Figure), this eliminates the hazard.

• The term AC remains 1 while B is changing, so no glitch can appear in the output.
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SIMULATION AND TESTING OF LOGIC CIRCUITS

• In logic design process, Logic circuits may be tested either by building them or by simulating them
on a computer.

• As logic circuits become more and more complex, it is very important to simulate a design before
building it.

Simulation is done for following reasons

(1) Verification that the design is logically correct

(2) Verification that the timing of the logic signals is correct

(3) Simulation of faulty components in the circuit as an aid to finding tests for the

circuits.

A simple simulator for combinational logic works as follows

• The circuit inputs are applied to the first set of gates in the circuit, and the outputs of those gates
are calculated.

• The outputs of the gates which changed in the previous step are fed into the next level of gate
inputs. If the input to any gate has changed, then the output of that gate is calculated.

Four-Valued Logic Simulator:

• The two logic values, 0 and 1, are not sufficient for simulating logic circuits.
• The value of a gate input or output may be unknown, and we will represent this unknown value
by X.

• If no logic signal at an input, as in the case of an open circuit we use the logic value Z to represent
an open circuit, or high impedance (hi-Z) connection.

The following Figure shows a typical simulation screen on a personal computer.

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The following Table shows AND and OR functions for four-valued logic simulation.

For an AND gate,

 If one of the inputs is 0, the output is always 0 regardless of the other input

 If one input is 1 and the other input is X then the output is X.

 If one input is 1 and the other input is Z then the output is X.

For an OR gate,

 If one of the inputs is 1, the output is 1 regardless of the other input

 If one input is 0 and the other input is X or Z, the output is unknown.

THREE STATE BUFFERS

• A gate output can only be connected to a limited number of other device inputs without degrading
the performance of a digital system.

• A simple buffer may be used to increase the driving capability of a gate output.

The following Figure shows a three-statebuffer and its logical equivalent

Fig: Three state buffer

• When the enable input B is 1, the output C equals A.

• when B is 0, the output C acts like an open circuit. This is called as high-impedance ( Hi-Z ) state.

• Three-state buffers are also called tri-state buffers

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Types of three-state buffers.

• In Figures (a) and (b) the buffer output is enabled when B = 1 and disabled when B = 0.

• In Figures (c) and (d) the buffer output is enabled when B = 0 and disabled when B = 1.
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MULTIPLEXERS

 A multiplexer is a data selector which has a group of data inputs , a group of control inputs and
single output.

 The control inputs are used to select one of the data inputs and connect it to the output terminal.

2-to-1 multiplexer

 When the control input A is 0, the switch is in the upper position and the MUX output is Z = I0.

 when A is 1, the switch is in the lower position and the MUX output is Z = I1.

 MUX acts like a switch that selects one of the data inputs (I0 or I1) and transmits it to the output

 The logic equation for the 2-to-1 MUX is

4 to 1 Multiplexer

For 4 to 1 multiplexer, 4 data inputs, 2 selection lines and 1 output is needed. The block diagram and
circuit diagram is shown below.
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• For selection inputs, A= 0, B=0, first AND gate alone is enabled and the output produced is

• For selection inputs, A= 0, B=1, second AND gate alone is enabled and the output produced is

• For selection inputs, A= 1, B=0, third AND gate alone is enabled and the output produced is

• For selection inputs, A= 1, B=1, forth AND gate alone is enabled and the output produced is

Truth table for 4 to 1 MUX is shown below

Figure shows diagrams for a 4-to-1 multiplexer, 8-to-1 multiplexer, and 2n-to-1 multiplexer.
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8 to 1 Multiplexer IC 74151

Decoder
A decoder is a multiple-input, multiple-output combinational logic circuit. It converts the n bit data inputs
into the coded 2n outputs.

2 to 4 binary decoder
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• The block diagram and Logic diagram is shown above. A and B are the two inputs and the output
produced is one of the minterms.

• The circuit diagram has two inverters, which will provide the complement of two inputs A and B.

• Each AND gates generates one of the minters as an output.

Truth table

From the above truth table, the operation can be understood.

• When both the inputs A and B are 0, Y0 will be at active HIGH or logic 1 and the remaining
output pins are active LOW or logic 0.

• When A = 0 and B = 1, Y1 is at HIGH.

• When A = 1 and B = 0, Y2 is at HIGH.

• When A = 1 and B = 1, Y3 is at HIGH.

3-to-8-line decoder
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Problem: Show how using a 3-to8 decoder and multi-input OR gates following Boolean expression can
be realized simultaneously.
F1 (A, B, C) = ∑m (0, 4, 6)
F2 (A, B, C) = ∑m (0, 5)
F3 (A, B, C) = ∑m (1, 2, 3, 7).

Solution:

Seven-Segment Display
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Common Anode Seven-Segment Display

Common Cathode Seven-Segment Display

BCD to 7 Segment Decoder

• It converts BCD into 7 segment outputs

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Seven-Segment Decoder IC 7446 with Seven –Segment Display

Truth Table
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ENCODERS
An encoder (converts an active input signal to a coded output signal) performs the inverse function of a
decoder.

4 to 2 Encoder

Truth Table

Fig shows 4 to 2 line Encoder. It has 4 inputs Y0,Y1,Y2,Y3 and 2 outputs A0,A1.
From the truth table it is clear that
If inputs Y3=0,Y2=0,Y1=0,Y0=1 then outputs A1=0 and A0=0.
If inputs Y3=0,Y2=0,Y1=1,Y0=0 then outputs A1=0 and A0=1.
If inputs Y3=0,Y2=1,Y1=0,Y0=0 then outputs A1=1 and A0=0.
If inputs Y3=1,Y2=0,Y1=0,Y0=0 then outputs A1=1 and A0=1.

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2A1=Y3+Y2
A0=Y3+Y1
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8 to 3 Encoder

Fig shows 8 to 3 line Encoder. It has 8 inputs D0,D1,D2,D3,D4,D5,D6,D7 and 3 outputs Y2,Y1,Y0.

Truth Table

From the truth table it is clear that

If inputs D0=1,D1=0,D2=0,D3=0,D4=0,D5=0,D6=0,D7=0 then outputs Y2=0, Y1=0 and Y0=0.
If inputs D0=0,D1=1,D2=0,D3=0,D4=0,D5=0,D6=0,D7=0 then outputs Y2=0, Y1=0 and Y0=1.
If inputs D0=0,D1=0,D2=1,D3=0,D4=0,D5=0,D6=0,D7=0 then outputs Y2=0, Y1=1 and Y0=0.
If inputs D0=0,D1=0,D2=0,D3=1,D4=0,D5=0,D6=0,D7=0 then outputs Y2=0, Y1=1 and Y0=1.
If inputs D0=0,D1=0,D2=0,D3=0,D4=1,D5=0,D6=0,D7=0 then outputs Y2=1, Y1=0 and Y0=0.
If inputs D0=0,D1=0,D2=0,D3=0,D4=0,D5=1,D6=0,D7=0 then outputs Y2=1, Y1=0 and Y0=1.
If inputs D0=0,D1=0,D2=0,D3=0,D4=0,D5=0,D6=1,D7=0 then outputs Y2=1, Y1=1 and Y0=0.
If inputs D0=0,D1=0,D2=0,D3=0,D4=0,D5=0,D6=0,D7=1 then outputs Y2=1, Y1=1 and Y0=1.

From Truth table, we can write the Boolean functions for each output as
Y2=D7+D6+D5+D4
Y1=D7+D6+D3+D2
Y0=D7+D5+D3+D1
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PROGRAMMABLE LOGIC DEVICES (PLDs)

• A programmable logic device (PLD) is a digital integrated circuit capable of being programmed to
provide different logic functions.

Classification

• Programmable Read Only Memory (PROM)

• Programmable Array Logic (PAL)

• Programmable Logic Array (PLA)

An example of PLA circuit of a combinational circuit is shown below. As you can observe from the
circuit diagram, AND array consists of fuses, to program according to the user requirements.
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Example 1
Realize the Boolean expression
W = AB + AB’C’ + BC’ and
X = BC + A’BC’ + ABC using Programmable Logic Array.

Solution:

• There are three inputs(A, B, C) and two outputs(W, X). The complement of three inputs are
obtained through NOT gates.

• The given expression has six product terms.

• Two OR gate arrays are used at the output to realize the the two functions.
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Example 2
Realize a boolean functions
F1(A, B, C) = ∑ m(1, 3, 6, 7) and
F2(A, B, C) = ∑ m(0, 2, 4, 5) using PLA.

Solution

To obtain the expression, the given function is implemented using Karnaugh map.

Thus for the two obtained expressions, the PLA circuit is realized. There are three inputs(A, B, C) and two
outputs(F1, F2). In the obtained expressions, there are four product terms and so four AND gate array is
used. Two OR gates are used to generate the two boolean fuctions.

The realization of the given Boolean function is drawn below.

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Programmable Logic Arrays (PLA)

• In PLA the product terms of the input variables is realized by an AND array and the OR array to
form the output functions.

• Hence, a PLA implements a sum-of-products expression.

• PLA has “n” input lines and “m” output lines.

Fig: PLA Structure

Programmable Array Logic (PAL)

A PAL is a programmable logic array (PLA) in which the AND array is programmable and the OR array is
fixed.

Consider the PAL segment of the following Figure (a), used to realize the function 𝐼1𝐼′2 + 𝐼′1𝐼2. The X’s in
the following Figure (b) indicate that 𝐼1 𝑎𝑛𝑑 𝐼′2 lines are connected to the first AND gate, and The 𝐼′1𝑎𝑛𝑑
𝐼2 lines are connected to the other gate.