1.
Introduction to HDL (Verilog Overview & Syntax)
Goal: Understand Verilog modules, ports, and data types.
🔹 Basic Verilog Syntax
module and_gate (input a, input b, output y);
assign y = a & b;
endmodule
module defines the block
input, output are ports
assign defines logic (combinational)
2. Digital Logic Programming (Basic Circuits)
Goal: Implement basic gates using Verilog.
🔹 Example: OR Gate
module or_gate(input a, input b, output y);
assign y = a | b;
endmodule
🔹 Example: NOT Gate
module not_gate(input a, output y);
assign y = ~a;
endmodule
🔹 Example: 2:1 Multiplexer
module mux2x1(input a, input b, input sel, output y);
assign y = sel ? b : a;
endmodule
3. Arithmetic Operations (8-bit Adder, Multiplier, Divider)
Goal: Build arithmetic units using HDL.
🔹 8-bit Adder
module adder8(input [7:0] a, b, output [7:0] sum);
assign sum = a + b;
endmodule
🔹 8-bit Multiplier
module mult8(input [7:0] a, b, output [15:0] product);
assign product = a * b;
endmodule
🔹 8-bit Divider (Unsigned)
module div8(input [7:0] a, b, output [7:0] quotient, output [7:0] remainder);
assign quotient = a / b;
assign remainder = a % b;
endmodule
4. 8-bit ALU Design
Goal: Design an ALU supporting multiple operations.
🔹 ALU Code
module alu8(
input [7:0] a, b,
input [2:0] sel, // select line for operation
output reg [7:0] result
);
always @(*) begin
case(sel)
3'b000: result = a + b; // Add
3'b001: result = a - b; // Subtract
3'b010: result = a & b; // AND
3'b011: result = a | b; // OR
3'b100: result = a ^ b; // XOR
3'b101: result = ~a; // NOT A
3'b110: result = a << 1; // Shift Left
3'b111: result = a >> 1; // Shift Right
endcase
end
endmodule
5. 8-bit CPU Design (Simple CPU)
Goal: Build a basic CPU that fetches, decodes, and executes simple instructions.
🔹 Key Components:
PC (Program Counter)
IR (Instruction Register)
AC (Accumulator)
Simple Instruction Set (ADD, SUB, LDA, STA)
You'd need to:
Use FSM (Finite State Machine) for instruction cycle
Handle opcode, address, ALU, and memory access
This part is usually complex and modular — let me know if you want a simplified
CPU example.
6. 8-bit Register Design
Goal: Implement an 8-bit register that can store and return values.
module reg8(
input clk, load,
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk) begin
if (load)
q <= d;
end
endmodule
7. Memory Unit Design
Goal: Simulate memory read/write operations.
module memory(
input clk,
input [7:0] address,
input [7:0] write_data,
input mem_write, mem_read,
output reg [7:0] read_data
);
reg [7:0] mem [0:255]; // 256 x 8-bit memory
always @(posedge clk) begin
if (mem_write)
mem[address] <= write_data;
if (mem_read)
read_data <= mem[address];
end
endmodule
8. CPU and Memory Interfacing
Goal: Connect CPU (registers + ALU + PC + control) with memory module.
Use:
o memory.v from Step 7
o reg8.v and alu8.v from earlier
o FSM to orchestrate fetch-decode-execute cycle
✅ Suggested Workflow
Lab Task Files to Create Test with
AND, OR, NOT gate.v testbench.v
ALU alu8.v test_alu.v
Register reg8.v test_reg.v
Memory memory.v test_mem.v
CPU cpu.v + others Integrated testbench
Q9. Create micro-operations, register set, memory, and instruction set
✅ Register Set
Register Size Description
PC 12-bit Program Counter – holds next instruction address
AR 12-bit Address Register – holds memory address for current operation
IR 16-bit Instruction Register – holds fetched instruction
DR 16-bit Data Register – holds operand from memory
AC 16-bit Accumulator – main data register
E 1-bit Extension bit for overflow/carry
I 1-bit Addressing mode flag: 0 = direct, 1 = indirect
✅ Memory
Word size: 16 bits
Address space: 12 bits ⇒ 0 to 4095 locations
Memory is addressable and can store instructions or data.
✅ Instruction Format (16-bit)
| 15 | 14-12 | 11-0 |
| I | OPC | Addr |
I = Addressing mode (1-bit)
OPC = Opcode (3-bit)
Addr = 12-bit address
✅ Sample Instruction Set (Memory Reference Instructions)
Opcode
Mnemonic Operation
(Binary)
000 AND AC ← AC ∧ M[AR]
001 ADD AC ← AC + M[AR]
010 LDA AC ← M[AR]
011 STA M[AR] ← AC
100 BUN PC ← AR
101 BSA M[AR] ← PC; PC ← AR+1
M[AR] ← M[AR] + 1; if M[AR] = 0 then PC ← PC
110 ISZ
+1
🔹 Q10. Instruction Fetch Routine (Micro-Operations)
1. T0: AR ← PC
2. T1: IR ← M[AR], PC ← PC + 1
3. T2: Decode IR → OPC, I, Addr
4. T3: If I=1 then AR ← M[Addr] else AR ← Addr
5. Proceed to Execute Cycle based on OPC
🔹 Q11. Simulate Execution (Memory-Reference Instruction, I = 1)
Given:
Instruction stored at 026: memory[026] = (e.g.) 1XX082 (Assume opcode is
010 → LDA)
I = 1 (indirect mode)
memory[082] = 298₁₆
memory[298] = B8F2₁₆
AC = A937₁₆
💻 Step-by-step Simulation (LDA instruction):
Memory contents:
Address Content
902082 (binary form: 1 010 000010100010) ⇒ I = 1, OPC = 010 (LDA),
026
Addr = 082
082 298
298 B8F2
🧮 Micro-Operation Steps:
1. T0: AR ← PC = 026
2. T1: IR ← M[AR] = 902082; PC ← PC + 1 = 027
3. T2: Decode IR: I = 1, OPC = 010, Addr = 082
4. T3: I = 1 ⇒ AR ← M[082] = 298
5. T4: LDA ⇒ AC ← M[AR] = M[298] = B8F2
✅ Final Register States (after execution):
Register Value (Hex)
AC B8F2
DR B8F2
AR 298
IR 902082 (binary form: 101000000010) = 902082₁₆
PC 027
Q11. Simulation of a Memory Reference Instruction (I = 1, LDA)
Given:
Instruction Address: 026
Instruction Format: I OPC Address → 1 010 082 = LDA with indirect
addressing
memory[026] = 902082 → Binary = 1 010 000010100010
memory[082] = 298
memory[298] = B8F2
AC = A937
All values are in hexadecimal
🔁 Step-by-step Micro-Operations:
Step Operation Result (Hex)
T0 AR ← PC = 026 AR = 026
T1 IR ← M[AR] = 902082; PC ← PC + 1 IR = 902082, PC = 027
T2 Decode: OPC = 010 (LDA), I = 1, Address = 082
T3 I = 1 → AR ← M[082] = 298 AR = 298
T4 AC ← M[AR] = M[298] = B8F2 AC = B8F2, DR = B8F2
✅ Final Register Contents:
Register Value (Hex)
AC B8F2
DR B8F2
PC 027
AR 298
IR 902082 (can be split: I=1, OPC=010, Addr=082)
✅ Q12. Simulation of Register Reference Instructions
Initial Setup:
AC = A937
E=1
PC = 022
📘 Register Reference Instructions
These use IR[15-12] = 0111 and IR[11-0] as control bits for micro-operations.
Below are the effects of each:
Mnemonic Description Micro-Operation
CMA Complement AC AC ← AC̅
CLE Clear E E←0
CLA Clear AC AC ← 0
CME Complement E E ← E̅
INC Increment AC AC ← AC + 1
CIR Circulate Right AC + E (AC, E) ← Right shift 1
CIL Circulate Left AC + E (AC, E) ← Left shift 1
SPA Skip if AC is positive (MSB = 0) If AC[15] = 0 then PC ← PC + 1
SNA Skip if AC is negative (MSB = 1) If AC[15] = 1 then PC ← PC + 1
SZA Skip if AC is zero If AC == 0 then PC ← PC + 1
SZE Skip if E is zero If E == 0 then PC ← PC + 1
HLT Halt the program Stop execution
🔁 Apply Instructions One by One:
Let’s use AC = A937, E = 1, PC = 022 initially.
a. CMA → AC ← NOT A937 = 5668
AC = 5668, E = 1, PC = 022
b. CLE → E ← 0
AC = 5668, E = 0, PC = 022
c. CLA → AC ← 0
AC = 0000, E = 0, PC = 022
d. CME → E ← NOT 0 = 1
AC = 0000, E = 1, PC = 022
e. CIR → Right shift (AC:E = 0000:1) → 8000
Before: AC = 0000, E = 1
Combined: 0000 0000 0000 0001 → Right shift → 1000 0000 0000 0000
AC = 8000, E = 0
f. CIL → Left shift (AC:E = 8000:0) → 0000, E = 1
1000 0000 0000 0000 ← 1 → 0000 0000 0000 0000, E = 1
g. INC → AC = 0000 + 1 = 0001
AC = 0001, E = 1
h. SPA → AC is positive ⇒ Skip
MSB of AC = 0 → PC = PC + 1 = 023
i. SNA → AC not negative ⇒ Don’t skip
MSB = 0 → PC remains 023
j. SZA → AC ≠ 0 ⇒ No skip
AC = 0001 → PC = 023
k. SZE → E ≠ 0 ⇒ No skip
PC = 023
l. HLT → Halt
Final state captured.
✅ Final Register Contents:
Register Value
AC 0001
E 1
PC 023
AR N/A (depends on next fetch)
IR HLT (071000) or as defined
