UNIT 5

FIELD EFFECT TRANSISTOR

5.1 INTRODUCTION
1. The Field effect transistor is abbreviated as FET , it is an another semiconductor device like a
BJT which can be used as an amplifier or switch.
2. The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a
current controlled device. Unlike BJT a FET requires virtually no input current.
3. This gives it an extremely high input resistance , which is its most important advantage over a
bipolar transistor.
4. FET is also a three terminal device, labeled as source, drain and gate.
5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the counter
part of the base.
6. The material that connects the source to drain is referred to as the channel.

7. FET operation depends only on the flow of majority carriers ,therefore they are called uni polar
devices. BJT operation depends on both minority and majority carriers.

8. As FET has conduction through only majority carriers it is less noisy than BJT.

9. FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less
space than BJTs.

10. FET amplifiers have low gain bandwidth product due to the junction capacitive effects and
produce more signal distortion except for small signal operation.

11. The performance of FET is relatively unaffected by ambient temperature changes. As it has a
negative temperature coefficient at high current levels, it prevents the FET from thermal
breakdown. The BJT has a positive temperature coefficient at high current levels which leads to
thermal breakdown.

5.2 CLASSIFICATION OF FET:

There are two major categories of field effect transistors:

1. Junction Field Effect Transistors

2. MOSFETs

These are further sub divided in to P- channel and N-channel devices.

MOSFETs are further classified in to two types Depletion MOSFETs and Enhancement . MOSFETs
 When the channel is of N-type the JFET is referred to as an N-channel JFET ,when the channel is of
P-type the JFET is referred to as P-channel JFET.

The schematic symbols for the P-channel and N-channel JFETs are shown in the figure.

Fig 5.1 schematic symbols for the P-channel and N-channel JFET

5.3 CONSTRUCTION AND OPERATION OF N- CHANNEL FET

If the gate is an N-type material, the channel must be a P-type material.

CONSTRUCTION OF N-CHANNEL JFET

Fig 5.2 Construction of N-Channel JFET

A piece of N- type material, referred to as channel has two smaller pieces of P-type material
attached to its sides, forming PN junctions. The channel ends are designated as the drain and
source. And the two pieces of P-type material are connected together and their terminal is called
the gate. Since this channel is in the N-type bar, the FET is known as N-channel JFET.
OPERATION OF N-CHANNEL JFET:-

The overall operation of the JFET is based on varying the width of the channel to control the drain
current.

A piece of N type material referred to as the channel, has two smaller pieces of P type
material attached to its sites, farming PN –Junctions. The channel’s ends are designated the drain and
the source. And the two pieces of P type material are connected together and their terminal is called
the gate. With the gate terminal not connected and the potential applied positive at the drain negative
at the source a drain current Id flows. When the gate is biased negative with respective to the source
the PN junctions are reverse biased and depletion regions are formed. The channel is more lightly
doped than the P type gate blocks, so the depletion regions penetrate deeply into the channel. Since
depletion region is a region depleted of charge carriers it behaves as an Insulator. The result is that the
channel is narrowed. Its resistance is increased and Id is reduced. When the negative gate bias voltage
is further increased, the depletion regions meet at the center and Id is cut off completely.

There are two ways to control the channel width

1. By varying the value of Vgs

2. And by Varying the value of Vds holding Vgs constant

1 By varying the value of Vgs :-

We can vary the width of the channel and in turn vary the amount of drain
current. This can be done by varying the value of Vgs. This point is illustrated in the fig below. Here
we are dealing with N channel FET. So channel is of N type and gate is of P type that constitutes a
PN junction. This PN junction is always reverse biased in JFET operation .The reverse bias is applied
by a battery voltage Vgs connected between the gate and the source terminal i.e positive terminal
of the battery is connected to the source and negative terminal to gate.
1) When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving
immobile ions on the N and P sides , the region containing these immobile ions is known as
depletion regions.
2) If both P and N regions are heavily doped then the depletion region extends symmetrically on
both sides.
3) But in N channel FET P region is heavily doped than N type thus depletion region extends more
in N region than P region.
4) So when no Vds is applied the depletion region is symmetrical and the conductivity becomes
Zero. Since there are no mobile carriers in the junction.
5) As the reverse bias voltage is increases the thickness of the depletion region also increases. i.e.
the effective channel width decreases .
6) By varying the value of Vgs we can vary the width of the channel.

2 Varying the value of Vds holding Vgs constant :-

1) When no voltage is applied to the gate i.e. Vgs=0 , Vds is applied between source and drain the
electrons will flow from source to drain through the channel constituting drain current Id .
2) With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open .In response to a
small applied voltage Vds , the entire bar acts as a simple semi conductor resistor and the
current Id increases linearly with Vds .
3) The channel resistances are represented as rd and rs as shown in the fig.

4) This increasing drain current Id produces a voltage drop across rd which reverse biases the gate
to source junction,(rd> rs) .Thus the depletion region is formed which is not symmetrical .
 5) The depletion region i.e. developed penetrates deeper in to the channel near drain and less
towards source because Vrd >> Vrs. So reverse bias is higher near drain than at source.
6) As a result growing depletion region reduces the effective width of the channel. Eventually a
voltage Vds is reached at which the channel is pinched off. This is the voltage where the current
Id begins to level off and approach a constant value.
7) So, by varying the value of Vds we can vary the width of the channel holding Vgs constant.

When both Vgs and Vds is applied:-

It is of course in principle not possible for the channel to close Completely and there by reduce
the current Id to Zero for, if such indeed, could be the case the gate voltage Vgs is applied in the
direction to provide additional reverse bias

1) When voltage is applied between the drain and source with a battery Vdd, the electrons flow
from source to drain through the narrow channel existing between the depletion regions. This
constitutes the drain current Id, its conventional direction is from drain to source.
2) The value of drain current is maximum when no external voltage is applied between gate and
source and is designated by Idss.
 3) When Vgs is increased beyond Zero the depletion regions are widened. This reduces the
effective width of the channel and therefore controls the flow of drain current through the
channel.
4) When Vgs is further increased a stage is reached at which to depletion regions touch each
other that means the entire channel is closed with depletion region. This reduces the drain
current to Zero.

5.4 CHARACTERISTICS OF N-CHANNEL JFET

The family of curves that shows the relation between current and voltage are known as
characteristic curves.

There are two important characteristics of a JFET.

1) Drain or VI Characteristics
2) Transfer characteristics
1. Drain Characteristics:-
2. Drain characteristics shows the relation between the drain to source voltage Vds
and drain current Id. In order to explain typical drain characteristics let us consider the curve
with Vgs= 0.V.

1) When Vds is applied and it is increasing the drain current ID also increases linearly up to knee
point.
2) This shows that FET behaves like an ordinary resistor.This region is called as ohmic region.
3) ID increases with increase in drain to source voltage. Here the drain current is increased
slowly as compared to ohmic region.
 4)
5)
6)

4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias
voltage across the gate source junction .As a result of this depletion region grows in size thereby
reducing the effective width of the channel.

5) All the drain to source voltage corresponding to point the channel width is reduced to a
minimum value and is known as pinch off.

5) The drain to source voltage at which channel pinch off occurs is called pinch off voltage(Vp).
PINCH OFF Region:-

1) This is the region shown by the curve as saturation region.

2) It is also called as saturation region or constant current region. Because of the channel is
occupied with depletion region , the depletion region is more towards the drain and less
towards the source, so the channel is limited, with this only limited number of carriers are
only allowed to cross this channel from source drain causing a current that is constant in
this region. To use FET as an amplifier it is operated in this saturation region.
3) In this drain current remains constant at its maximum value IDSS.

4) The drain current in the pinch off region depends upon the gate to source voltage and is
given by the relation
Id =Idss [1-Vgs/Vp]2

This is known as shokley’s relation.

BREAKDOWN REGION:-

1) The region is shown by the curve .In this region, the drain current increases rapidly as the
drain to source voltage is increased.
2) It is because of the gate to source junction due to avalanche effect.
 3) The avalanche break down occurs at progressively lower value of VDS because the reverse
bias gate voltage adds to the drain voltage thereby increasing effective voltage across the
gate junction
This causes

1. The maximum saturation drain current is smaller

2. The ohmic region portion decreased.
4) It is important to note that the maximum voltage VDS which can be applied to FET is the
lowest voltage which causes available break down.
3. TRANSFER CHARACTERISTICS:-

These curves shows the relationship between drain current ID and gate to source voltage
VGS for different values of VDS.

1) First adjust the drain to source voltage to some suitable value , then increase the gate to
source voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and current ID on
the vertical axis. We shall obtain a curve like this.

3) As we know that if Vgs is more negative curves drain current to reduce . where Vgs is made
sufficiently negative, Id is reduced to zero. This is caused by the widening of the depletion
region to a point where it is completely closes the channel. The value of Vgs at the cutoff
point is designed as Vgsoff
 4) The upper end of the curve as shown by the drain current value is equal to I dss that is when
Vgs = 0 the drain current is maximum.

5) While the lower end is indicated by a voltage equal to Vgsoff

6) If Vgs continuously increasing , the channel width is reduced , then I d =0
7) It may be noted that curve is part of the parabola; it may be expressed as
Id=Idss[1-Vgs/Vgsoff]2

DIFFERENCE BETWEEN Vp AND Vgsoff –

Vp is the value of Vgs that causes the JFET to become constant current component, It is
measured at Vgs =0V and has a constant drain current of Id =Idss .Where Vgsoff is the value of Vgs that
reduces Id to approximately zero.

Why the gate to source junction of a JFET be always reverse biased ?

The gate to source junction of a JFET is never allowed to become forward biased because
the gate material is not designed to handle any significant amount of current. If the junction is allowed
to become forward biased, current is generated through the gate material. This current may destroy
the component.

There is one more important characteristic of JFET reverse biasing i.e. J FET ‘s have
extremely high characteristic gate input impedance. This impedance is typically in the high mega ohm
range. With the advantage of extremely high input impedance it draws no current from the source. The
high input impedance of the JFET has led to its extensive use in integrated circuits. The low current
requirements of the component makes it perfect for use in ICs. Where thousands of transistors must
be etched on to a single piece of silicon. The low current draw helps the IC to remain relatively cool,
thus allowing more components to be placed in a smaller physical area.

5.5 JFET PARAMETERS

The electrical behavior of JFET may be described in terms of certain parameters. Such parameters are
obtained from the characteristic curves.

A C Drain resistance(rd):

It is also called dynamic drain resistance and is the a.c.resistance between the drain and source
terminal,when the JFET is operating in the pinch off or saturation region.It is given by the ratio of small
change in drain to source voltage ∆Vds to the corresponding change in drain current ∆Id for a
constant gate to source voltage Vgs.

Mathematically it is expressed as rd=∆Vds/ ∆Id where Vgs is held constant.

TRANCE CONDUCTANCE (gm):

It is also called forward transconductance . It is given by the ratio of small change in drain current (∆I d)
to the corresponding change in gate to source voltage (∆V ds)

Mathematically the transconductance can be written as

gm=∆Id/∆Vds

AMPLIFICATION FACTOR (µ)

It is given by the ratio of small change in drain to source voltage (∆V ds) to the corresponding change in
gate to source voltage (∆Vgs)for a constant drain current (Id).

Thus µ=∆Vds/∆Vgs when Id held constant

The amplification factor µ may be expressed as a product of transconductance (g m)and ac drain

resistance (rd)

µ=∆Vds/∆Vgs=gm rd

5.5 THE FET SMALL SIGNAL MODEL

The linear small signal equivalent circuit for the FET can be obtained in a manner similar to
that used to derive the corresponding model for a transistor.

We can express the drain current iD as a function f of the gate voltage and drain voltage V ds.

Id =f(Vgs,Vds)------------------(1)

The transconductance gm and drain resistance rd:-

If both gate voltage and drain voltage are varied, the change in the drain current is
approximated by using taylors series considering only the first two terms in the expansion

∆id= |vds=constant .∆vgs |vgs=constant∆vds

we can write ∆id=id

∆vgs=vgs

∆vds=vds

Id=gm v Vds→(1)

Where gm= |Vds |Vds

 gm= |Vds

Is the mutual conductance or transconductance .It is also called as gfs or yfs common source forward
conductance .

The second parameter rd is the drain resistance or output resistance is defined as

rd= |Vgs |Vgs= |Vgs

rd= |Vgs

The reciprocal of the rd is the drain conductance gd .It is also designated by Yos and Gos and
called the common source output conductance . So the small signal equivalent circuit for FET can be
drawn in two different ways.

1.small signal current –source model

2.small signal voltage-source model.

A small signal current –source model for FET in common source configuration can be drawn
satisfying Eq→(1) as shown in the figure(a)

This low frequency model for FET has a Norton’s output circuit with a dependent current
generator whose magnitude is proportional to the gate-to –source voltage. The proportionality factor
is the transconductance ‘gm’. The output resistance is ‘rd’. The input resistance between the gate and
source is infinite, since it is assumed that the reverse biased gate draws no current. For the same
reason the resistance between gate and drain is assumed to be infinite.

The small signal voltage-source model is shown in the figure(b).

This can be derived by finding the Thevenin’s equivalent for the output part of fig(a) .

These small signal models for FET can be used for analyzing the three basic FET amplifier
configurations:

1.common source (CS) 2.common drain (CD) or source follower

3. common gate(CG).
(a)Small Signal Current source model for FET (b)Small Signal voltage source model for FET

Here the input circuit is kept open because of having high input impedance and the output
circuit satisfies the equation for ID

5.7 MOSFET
We now turn our attention to the insulated gate FET or metal oxide semi conductor FET which is
having the greater commercial importance than the junction FET.

Most MOSFETS however are triodes, with the substrate internally connected to the source. The circuit
symbols used by several manufacturers are indicated in the Fig below.

(a) Depletion type MOSFET (b) Enhancement type MOSFET

Both of them are P- channel

Here are two basic types of MOSFETS

(1) Depletion type (2) Enhancement type MOSFET.

D-MOSFETS can be operated in both the depletion mode and the enhancement mode. E MOSFETS
are restricted to operate in enhancement mode. The primary difference between them is their physical
construction.
The construction difference between the two is shown in the fig given below.

As we can see the D MOSFET have physical channel between the source and drain
terminals(Shaded area)

The E MOSFET on the other hand has no such channel physically. It depends on the gate voltage
to form a channel between the source and the drain terminals.

Both MOSFETS have an insulating layer between the gate and the rest of the component. This
insulating layer is made up of SIO2 a glass like insulating material. The gate material is made up of
metal conductor .Thus going from gate to substrate, we can have metal oxide semi conductor which is
where the term MOSFET comes from.

Since the gate is insulated from the rest of the component, the MOSFET is sometimes
referred to as an insulated gate FET or IGFET.

The foundation of the MOSFET is called the substrate. This material is represented in the schematic
symbol by the center line that is connected to the source.

In the symbol for the MOSFET, the arrow is placed on the substrate. As with JFET an arrow pointing in
represents an N-channel device, while an arrow pointing out represents p-channel device.

CONSTRUCTION OF AN N-CHANNEL MOSFET:-

The N- channel MOSFET consists of a lightly doped p type substance into which two heavily doped
n+ regions are diffused as shown in the Fig. These n+ sections , which will act as source and drain.
A thin layer of insulation silicon dioxide (SIO2) is grown over the surface of the structure, and
holes are cut into oxide layer, allowing contact with the source and drain. Then the gate metal area is
overlaid on the oxide, covering the entire channel region.Metal contacts are made to drain and source
and the contact to the metal over the channel area is the gate terminal.The metal area of the gate, in
conjunction with the insulating dielectric oxide layer and the semiconductor channel, forms a parallel
plate capacitor. The insulating layer of sio2

Is the reason why this device is called the insulated gate field effect transistor. This layer results in an
extremely high input resistance (10 10 to 10power 15ohms) for MOSFET.

5.7.1 DEPLETION MOSFET

The basic structure of D –MOSFET is shown in the fig. An N-channel is diffused between source and
drain with the device an appreciable drain current IDSS flows foe zero gate to source voltage, Vgs=0.

Depletion mode operation:-

1) The above fig shows the D-MOSFET operating conditions with gate and source terminals shorted
together(VGS=0V)

2) At this stage ID= IDSS where VGS=0V, with this voltage VDS, an appreciable drain current IDSS
flows.

3) If the gate to source voltage is made negative i.e. VGs is negative .Positive charges are induced in
the channel through the SIO2 of the gate capacitor.

4) Since the current in a FET is due to majority carriers(electrons for an N-type material) , the
induced positive charges make the channel less conductive and the drain current drops as Vgs is
made more negative.

5) The re distribution of charge in the channel causes an effective depletion of majority carriers ,
which accounts for the designation depletion MOSFET.

6) That means biasing voltage Vgs depletes the channel of free carriers This effectively reduces the
width of the channel , increasing its resistance.

7) Note that negative Vgs has the same effect on the MOSFET as it has on the JFET.

8) As shown in the fig above, the depletion layer generated by Vgs (represented by the white space
between the insulating material and the channel) cuts into the channel, reducing its width. As a
result ,Id<Idss.The actual value of ID depends on the value of Idss,Vgs(off) and Vgs.

Enhancement mode operation of the D-MOSFET:-

1) This operating mode is a result of applying a positive gate to source voltage Vgs to the device.
2) When Vgs is positive the channel is effectively widened. This reduces the resistance of the
channel allowing ID to exceed the value of IDSS
3) When Vgs is given positive the majority carriers in the p-type are holes. The holes in the p type
substrate are repelled by the +ve gate voltage.
 4) At the same time, the conduction band electrons (minority carriers) in the p type material are
attracted towards the channel by the +gate voltage.
5) With the build up of electrons near the channel , the area to the right of the physical channel
effectively becomes an N type material.
6) The extended n type channel now allows more current, Id> Idss

Characteristics of Depletion MOSFET:-

The fig. shows the drain characteristics for the N channel depletion type MOSFET

1) The curves are plotted for both Vgs positive and Vgs negative voltages
.
2) When Vgs=0 and negative the MOSFET operates in depletion mode when Vgs is positive ,the
MOSFET operates in the enhancement mode.
3) The difference between JFET and D MOSFET is that JFET does not operate for positive values of
Vgs.

4) When Vds=0, there is no conduction takes place between source to drain, if Vgs<0 and Vds>0
then Id increases linearly.

5) But as Vgs,0 induces positive charges holes in the channel, and controls the channel width. Thus
the conduction between source to drain is maintained as constant, i.e. Id is constant.

6) If Vgs>0 the gate induces more electrons in channel side, it is added with the free electrons
generated by source. again the potential applied to gate determines the channel width and
maintains constant current flow through it as shown in Fig
TRANSFER CHARACTERISTICS:-

The combination of 3 operating states i.e. Vgs=0V, VGs<0V, Vgs>0V is represented by the D
MOSFET transconductance curve shown in Fig.

1) Here in this curve it may be noted that the region AB of the characteristics similar to that of
JFET.

2) This curve extends for the positive values of Vgs

3) Note that Id=Idss for Vgs=0V when Vgs is negative,Id< Idss when Vgs= Vgs(off) ,Id is reduced to
approximately omA.Where Vgs is positive Id>Idss.So obviously Idss is not the maximum possible
value of Id for a MOSFET.

4) The curves are similar to JFET so thet the D MOSFET have the same transconductance equation.

5.7.2 E-MOSFETS

The E MOSFET is capable of operating only in the enhancement mode.The gate potential must be
positive w.r.t to source.

1) when the value of Vgs=0V, there is no channel connecting the source and drain materials.

2) As aresult , there can be no significant amount of drain current.

3) When Vgs=0, the Vdd supply tries to force free electrons from source to drain but the presence
of p-region does not permit the electrons to pass through it. Thus there is no drain current at
Vgs=0,

4) If Vgs is positive, it induces a negative charge in the p type substrate just adjacent to the SIO2
layer.

5) As the holes are repelled by the positive gate voltage, the minority carrier electrons attracted
toward this voltage. This forms an effective N type bridge between source and drain providing a
path for drain current.

6) This +ve gate voltage forma a channel between the source and drain.

7) This produces a thin layer of N type channel in the P type substarate.This layer of free electrons
is called N type inversion layer.
8) The minimum Vgs which produces this inversion layer is called threshold voltage and is
designated by Vgs(th).This is the point at which the device turns on is called the threshold
voltage Vgs(th)
9) When the voltage Vgs is <Vgs (th) no current flows from drain to source.

10) How ever when the voltage Vgs > Vgs (th) the inversion layer connects the drain to source and
we get significant values of current.

CHARACTERISTICS OF E MOSFET:-

1. DRAIN CHARACTERISTICS

The volt ampere drain characteristics of an N-channel enhancement mode MOSFET are given in the

fig.
 2. TRANSFER CHARACTERISTICS:-

1) The current Idss at Vgs≤ 0 is very small beinf of the order of a few nano amps.
2) As Vgs is made +ve , the current Id increases slowly at forst, and then much more rapidly with
an increase in Vgs.
3) The standard transconductance formula will not work for the E MOSFET.
4) To determine the value of ID at a given value of VGs we must use the following relation
Id =K[Vgs-Vgs(Th)]2

Where K is constant for the MOSFET . found as

K=

From the data specification sheets, the 2N7000 has the following ratings.

Id(on)= 75mA(minimum).

And Vgs(th)=0.8(minimum)

5.8 APPLICATION OF MOSFET

One of the primary contributions to electronics made by MOSFETs can be found in the area of
digital (computer electronics). The signals in digital circuits are made up of rapidly switching dc
levels. This signal is called as a rectangular wave ,made up of two dc levels (or logic levels). These
logic levels are 0V and +5V.
 A group of circuits with similar circuitry and operating characteristics is referred to as a logic
family. All the circuits in a given logic family respond to the same logic levels, have similar speed
and power-handling capabilities , and can be directly connected together. One such logic family is
complementary MOS (or CMOS) logic. This logic family is made up entirely of MOSFETs.

5.9 BIASING FET:-

For the proper functioning of a linear FET amplifier, it is necessary to maintain the
operating point Q stable in the central portion of the pinch off region The Q point should be
independent of device parameter variations and ambient temperature variations

This can be achieved by suitably selecting the gate to source voltage VGS and drain current ID
which is referred to as biasing

JFET biasing circuits are very similar to BJT biasing circuitsThe main difference between
JFET circuits and BJT circuits is the operation of the active components themselves

There are mainly two types of Biasing circuits

1) Self bias
2) Voltage divider bias.

5.9.1 SELF BIAS

Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate. A self
bias circuit is shown in the fig. Self bias is the most common type of JFET bias. This JFET must be
operated such that gate source junction is always reverse biased. This condition requires a negative
VGS for an N channel JFET and a positive VGS for P channel JFET. This can be achieved using the self
bias arrangement as shown in Fig. The gate resistor RG doesn’t affect the bias because it has essentially
no voltage drop across it, and : the gate remains at 0V .RG is necessary only to isolate an ac signal from
ground in amplifier applications. The voltage drop across resistor RS makes gate source junction
reverse biased.
 For the dc analysis coupling capacitors are open circuits.

For the N channel FET in Fig (a)

IS produces a voltage drop across RS and makes the source positive w.r.t ground. In any JFET circuit all
the source current passes through the device to the drain circuit .This is due to the fact that there is no
significant gate current.

We can define source current as IS = ID

(VG =0 because there is no gate current flowing in RG So VG across RG is zero)

VG =0 then VS= ISRS =ID RS

VGS = VG-VS =0-ID RS=- ID RS

DC analysis of self Bias:-

In the following DC analysis, the N channel J FET shown in the fig. is used for illustration.

For DC analysis we can replace coupling capacitors by open circuits and we can also replace the resistor
RG by a short circuit equivalent.:. IG = 0.The relation between ID and VGS is given by

Id=Idss[1- ]2

VGS for N channel JFET is =-id Rs

Substuting this value in the above equation

Id=Idss[1- ]2

Id=Idss[1+ ]2

For the N-chanel FET in the above figure

 Is produces a voltage drop across Rs and makes the source positive w.r.t ground in any JFET circuit
all the source current passes through the device to drain circuit this is due to the fact that there is no
significant gate current. Therefore we can define source current as Is=Id and Vg=0 then

Vs= Is Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawing the self bias line:-

Typical transfer characteristics for a self biased JFET are shown in the fig.

The maximum drain current is 5mA and the gate source cut off voltage is -3V. This means the gate
voltage has to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self bias
line.

Let us assume RS = 500Ω

With this Rs , we can plot two points corresponding to ID = 0 and Id = IDSS

for ID = 0

VGS = -ID RS

VGS = 0X (500.Ω) = 0V

So the first point is (0 ,0)

( Id, VGS)
 For ID= IDSS=5mA

VGS = (-5mA) (500 Ω) = -3V

So the 2nd Point will be (5mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will
intersect the transconductance curve and it is known as self bias line.The intersection point gives the
operating point of the self bias JFET for the circuit.

At Q point , the ID is slightly > than 2mA and VGS is slightly > -1V. The Q point for the self bias
JFET depends on the value of Rs.If Rs is large, Q point far down on the transconductance curve ,ID is
small, when Rs is small Q point is far up on the curve , ID is large.

5.9.2 VOLTAGE DIVIDER BIAS:-

The fig. shows N channel JFET with voltage divider bias. The voltage at the source of JFET must
be more positive than the voltage at the gate in order to keep the gate to source junction reverse
biased. The source voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the
voltage divider formula.

Vg= Vdd

For dc analysis
 Applying KVL to the input circuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS :: IS = ID

Applying KVL to the input circuit we get

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS

VDS = VDD-ID ( RD +RS )

The Q point of a JFET amplifier , using the voltage divider bias is

IDQ = IDSS [1-VGS/VP]2

VDSQ = VDD-ID ( RD+RS )

COMPARISON OF MOSFET WITH JFET

a. In enhancement and depletion types of MOSFET, the transverse electric field induced
across an insulating layer deposited on the semiconductor material controls the
conductivity of the channel.

b. In the JFET the transverse electric field across the reverse biased PN junction controls the
conductivity of the channel.
 c. The gate leakage current in a MOSFET is of the order of 10-12A. Hence the input resistance
of a MOSFET is very high in the order of 1010 to 1015 Ω. The gate leakage current of a JFET
is of the order of 10-9A., and its input resistance is of the order of 108Ω.

d. The output characteristics of the JFET are flatter than those of the MOSFET, and hence the
drain resistance of a JFET (0.1 to 1MΩ) is much higher than that of a MOSFET (1 to 50kΩ).

e. JFETs are operated only in the depletion mode. The depletion type MOSFET may be
operated in both depletion and enhancement mode.

f. Comparing to JFET, MOSFETs are easier to fabricate.

g. Special digital CMOS circuits are available which involve near zero power dissipation and
very low voltage and current requirements. This makes them suitable for portable
systems.

FET AMPLIFIERS
5.10 INTRODUCTION
Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and high input
impedence. Because of high input impedence and other characteristics of JFETs they are preferred over
BJTs for certain types of applications.

There are 3 basic FET circuit configurations:

i)Common Source
ii)Common Drain
iii)Common Gain
Similar to BJT CE,CC and CB circuits, only difference is in BJT large output collector current is
controlled by small input base current whereas FET controls output current by means of small input
voltage. In both the cases output current is controlled variable.
FET amplifier circuits use voltage controlled nature of the JFET. In Pinch off region, ID depends
only on VGS.
5.11 Common Source (CS) Amplifier

Fig. 5.1 (a) CS Amplifier (b) Small-signal equivalent circuit

A simple Common Source amplifier is shown in Fig. 5.1(a) and associated small signal equivalent circuit
using voltage-source model of FET is shown in Fig. 5.1(b)

Voltage Gain
Source resistance (RS) is used to set the Q-Point but is bypassed by CS for mid-frequency operation.
From the small signal equivalent circuit ,the output voltage
VO = -RDµVgs(RD + rd)
Where Vgs = Vi , the input voltage,
Hence, the voltage gain,
AV = VO / Vi = -RDµ(RD + rd)
Input Impedence
From Fig. 5.1(b) Input Impedence is
Zi = RG
For voltage divider bias as in CE Amplifiers of BJT
RG = R1 ║ R2
Output Impedance
Output impedance is the impedance measured at the output terminals with the input voltage V I = 0
From the Fig. 5.1(b) when the input voltage Vi = 0, Vgs = 0 and hence
µ Vgs = 0
The equivalent circuit for calculating output impedence is given in Fig. 5.2.
Output impedence Zo = rd ║ RD
Normally rd will be far greater than RD . Hence Zo ≈ RD

5.12 Common Drain Amplifier

A simple common drain amplifier is shown in Fig. 5.2(a) and associated small signal equivalent circuit
using the voltage source model of FET is shown in Fig. 5.2(b).Since voltage Vgd is more easily
determined than Vgs, the voltage source in the output circuit is expressed in terms of V gs and Thevenin’s
theorem.

Fig. 5.2 (a)CD Amplifier (b)Small-signal equivalent circuit

Voltage Gain
The output voltage,
VO = RSµVgd / (µ + 1) RS + rd
Where Vgd = Vi the input voltage.
Hence, the voltage gain,
Av = VO / Vi = RSµ / (µ + 1) RS + rd
Input Impedence
From Fig. 5.2(b), Input Impedence Zi = RG
Output Impedence
From Fig. 5.2(b), Output impedence measured at the output terminals with input voltage V i = 0 can be
calculated from the following equivalent circuit.
As Vi = 0: Vgd = 0: µvgd / (µ + 1) = 0
Output Impedence
 ZO = rd / (µ + 1) ║RS
When µ » 1
ZO = ( rd / µ) ║RS = (1/gm) ║RS

5.13 BIASING FET

For the proper functioning of a linear FET amplifier, it is necessary to maintain the
operating point Q stable in the central portion of the pinch off region The Q point should be
independent of device parameter variations and ambient temperature variations

This can be achieved by suitably selecting the gate to source voltage VGS and drain current ID which is
referred to as biasing

JFET biasing circuits are very similar to BJT biasing circuitsThe main difference between JFET
circuits and BJT circuits is the operation of the active components themselves

There are mainly two types of Biasing circuits

1. Self bias
2. Voltage divider bias.

5.13.1. SELF BIAS:-

Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate.

A self bias circuit is shown in the fig 5.3

 Self bias is the most common type of JFET bias. This JFET must be operated such that gate
source junction is always reverse biased. This condition requires a negative VGS for an N channel JFET
and a positive VGS for P channel JFET. This can be achieved using the self bias arrangement as shown in
Fig 5.3. The gate resistor RG doesn’t affect the bias because it has essentially no voltage drop across it,
and : the gate remains at 0V .RG is necessary only to isolate an ac signal from ground in amplifier
applications. The voltage drop across resistor RS makes gate source junction reverse biased.

DC analysis of self Bias:-

In the following DC analysis , the N channel J FET shown in the fig5.4. is used for illustration.

For DC analysis we can replace coupling capacitors by open circuits and we can also replace the
resistor RG by a short circuit equivalent.

:. IG = 0

The relation between ID and VGS is given by

Id=Idss[1- ]2

VGS for N channel JFET is =-id Rs

Substuting this value in the above equation

Id=Idss[1- ]2

Id=Idss[1+ ]2
For the N-chanel FET in the above figure

Is produces a voltage drop across Rs and makes the source positive w.r.t ground

in any JFET circuit all the source current passes through the device to drain circuit this is due to the fact
that there is no significant gate current

therefore we can define source current as Is=Id and Vg=0 then

Vs= Is Rs =IdRs

Vgs=Vg-Vs=0-IdRs=-IdRs

Drawing the self bias line:-

Typical transfer characteristics for a self biased JFET are shown in the fig5.5.

The maximum drain current is 6mA and the gate source cut off voltage is -3V. This means the gate
voltage has to be between 0 and -3V.

Now using the equation VGS = -IDRS and assuming RS of any suitable value we can draw the self bias
line.

Let us assume RS = 500Ω

With this Rs , we can plot two points corresponding to ID = 0 and Id = IDSS

for ID = 0

VGS = -ID RS

VGS = 0X (500.Ω) = 0V
 So the first point is (0 ,0)

( Id, VGS)

For ID= IDSS=6mA

VGS = (-6mA) (500 Ω) = -3V

So the 2nd Point will be (6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will
intersect the transconductance curve and it is known as self bias line. The intersection point gives the
operating point of the self bias JFET for the circuit.

At Q point , the ID is slightly > than 2mA and VGS is slightly > -1V. The Q point for the self bias
JFET depends on the value of Rs.If Rs is large, Q point far down on the transconductance curve ,ID is
small, when Rs is small Q point is far up on the curve , ID is large.

5.13.2 VOLTAGE DIVIDER BIAS:-

The fig5.6 shows N channel JFET with voltage divider bias. The voltage at the source of JFET
must be more positive than the voltage at the gate in order to keep the gate to source junction reverse
biased. The source voltage is

VS = IDRS

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the
voltage divider formula.

Vg= Vdd
 For dc analysis fig 5.5

Applying KVL to the input circuit

VG-VGS-VS =0

:: VGS = VG-Vs=VG-ISRS

VGS = VG-IDRS :: IS = ID

Applying KVL to the input circuit we get

VDS+IDRD+VS-VDD =0

::VDS = VDD-IDRD-IDRS

VDS = VDD-ID ( RD +RS )

The Q point of a JFET amplifier , using the voltage divider bias is

IDQ = IDSS [1-VGS/VP]2

VDSQ = VDD-ID ( RD+RS )

5.14 JFET AS A VVR OR VDR

Let us consider the drain characteristics of FET as shown in the fig.
 In this characteristics we can see that in the region before pinch off voltage, drain
characteristics are linear, i.e. FET operation is linear. In this region the FET is useful as a voltage
controlled resistor,i.e. the drain to source resistance is controlled by the bias voltage VGS.( In this
region only FET behaves like an ordinary resistor This resistances can be varied by VGS ) .The operation
of FET in the region is useful in most linear applications of FET.In such an application the FET is also
referred to as a voltage variable resistor (VVR) or voltage dependent resistor (VDR).

The drain to source conductance ( rd )

gd= for small values of VDS which may also be expressed as

gd=gd0(1- )1/2)

Where gd0 is the value of drain conductance

When the variation of the rd with VGS can be closely approximated by the expression

rd= ) Where ro = drain resistance at zero gate bias.K = a constant, dependent upon FET
type.

5.14.1 APPLICATION OF VVR

The VVR property of FET can be used to vary the voltage gain of a multistage amplifier A, as the
signal level is increased. This action is called AGC automatic gain control. A typical arrangement is
shown in the fig.
 Here maximum value of signal is taken rectified; filter to produce a DC voltage proportional to
the output signal level. This voltage is applied to the gate of JFET, this causing the resistance between
drain and source to change. As this resistance is connected across RE, so effective RE also changes
according to change in the drain to source resistance. When output signal level increases, the drain to
source resistance rd increases, increasing effective RE. Increase in RE causes the gain of transistor Q1
to decrease, reducing the output signal. Exactly reverse process takes place when output signal level
decreased.

:: The output signal level is maintained constant. It is to be noted that the DC bias conditions of
Q1 are not affected by JFET since FET is isolated from Q1 by capacitor C2
 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

2.6 SILICON CONTROLLED RECTIFIER (SCR)

The SCR stand for Silicon Control Rectifier, it is used in industries because it can
handle high values of current and voltage.
Three terminals
• Anode - P-layer
• Cathode - N-layer (opposite end)
• Gate - P-layer near the cathode

Three junctions - four layers

Connect power such that the anode is positive with respect to the cathode - no current
will flow
A silicon controlled rectifier is a semiconductor device that acts as a true electronic
switch. It can change alternating current and at the same time can control the amount
of power fed to the load. SCR combines the features of a rectifier and a transistor.

Figure 2.6.1 Basic Structure, equivalent transistor model and symbol of SCR
[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 110]

When a p n junction is added to a junction transistor the resulting three p n junction

device is called a SCR. ordinary rectifier (p n) and a junction transistor (n p n)
combined in one unit to form p n p n device.
Three terminals are taken: one from the outer p- type material called anode a second
from the outer n- type material called cathode K and the third from the base of
transistor called Gate. GSCR is a solid state equivalent of thyratron. The gate anode
and cathode of SCR correspond to the grid plate and cathode of thyratron SCR is
called thyristor.

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

Working Principle
Load is connected in series with anode the anode is always kept at positive
potential w.r.t cathode.

SCR Operation / Working

The Silicon Control Rectifier SCR start conduction when it is forward biased. For this
purpose the cathode is kept at negative and anode at positive. When positive clock
pulse is applied at the gate the SCR turns ON.
When forward bias voltage is applied to the Silicon Control Rectifier SCR, the
junction J1 and J3 become forward bias while the junction J2 become reverse bias.

When we apply a clock pulse at the gate terminal, the junction J2 become forward bias
and the Silicon Control Rectifier SCR start conduction. The Silicon Control Rectifier
SCR turn ON and OFF very quickly, At the OFF state the Silicon Control Rectifier
SCR provide infinity resistance and in ON state, it offers very low resistance, which is
in the range of 0.01O to 1O.

SCR Firing & Triggering

The Silicon Control Rectifier SCR is normally operated below the forward break over
voltage (VBO). To turn ON the Silicon Control Rectifier SCR we apply clock pulse at
the gate terminal which called triggering of Silicon Control Rectifier, but when the
Silicon Control Rectifier SCR turned ON, now if we remove the triggering voltage, the
Silicon Control Rectifier SCR will remain in ON state. This voltage is called Firing
voltage

Break over Voltage

It is the minimum forward voltage gate being open at which SCR starts conducting
heavily i.e turned on.

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

Peak Reverse Voltage (PRV)

It is the maximum reverse voltage applied to an SCR without conducting in the reverse
direction

Holding Current

It is the maximum anode current gate being open at which SCR is turned off from on
conditions.

V-I Characteristics of SCR

Figure 2.6.2 V-I Characteristics of SCR

[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 110]

Forward Characteristics

When anode is +vew.r.t cathode the curve between V &I is called Forward
characteristics. OABC is the forward characteristics of the SCR at Ig =0. if the
suppliedvoltage is increased from zero point A is reached .SCR starts
conducting voltage across SCR suddenly drops (dotted curve AB) most of
supply voltage appears across RL
Reverse Characteristics

When anode is –ve w.r.t cathode the curve b/w V&I is known as reverse
characteristics reverse voltage come across SCR when it is operated with ac supply

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

reverse voltage is increased anode current remains small avalanche breakdown occurs
and SCR starts conducting heavily is known as reverse breakdown voltage.

Application

 SCR as a switch
 SCR Half and Full wave rectifier
 SCR as a static contactor
 SCR for power control
 SCR for speed control of d.c. shunt motor
 Over light detector

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 UNIT II
PHASE-CONTROLLED CONVERTERS
1. APPLICATION OF CONTROLLED RECTIFIER

 Steel rolling mills, paper mills, printing presses and textile mills employing dc motor drives.
 Traction systems working on DC
 Electrochemical and electrometallurgical processes
 Magnet power supplies
 Portable hand tool drives
 HVDC transmission

2. ONE PULSE CONVERTER

SINGLE PHASE HALF WAVE CONTROLLED RECTIFIER WITH R LOAD

Single Phase Half Wave Controlled Rectifier with R Load

During positive half cycle
 The anode is positive with respect to its cathode, and the thyristor is said to be forward biased.
 When T is triggered at wt=α, T conducts and the input voltage appears across the load.
 During the period α< wt<π, we can get the output voltage and current.
During negative half cycle
 The thyristor is negative with respect to its cathode, and T is said to be reverse biased.
  T blocks the flow of load current and no voltage is applied across the load R.
 By varying the firing angle α, the output voltage can be controlled.

SINGLE PHASE HALF WAVE CONTROLLED RECTIFIER WITH R-L LOAD

At wt=α
T is turned on by applying the gate signal. The load voltage vo at once becomes equal to source
voltage vs.
But inductance L forces the load or output current io rise gradually.
After sometime io reaches maximum value the then begins to decrease.
 At wt= π
vo is zero but io is not zero beacause of the load inductance L.
 After wt= π
After wt= π, SCR is subjected to reverse anode voltage, but it will not be turned off as the
load
current io is not less than the holding current.
At some angle β>π, io reduces to zero and T is turned off as already it is reverse biased.
 After wt=β
After wt=β, vo=0 and io=0.
Angle β is called extinction angle and γ= β-α is called the conduction angle.
SINGLE PHASE HALF WAVE CONTROLLED RECTIFIER WITH R-L LOAD AND FREE
WHEELING DIODE
 At wt=0, source voltage is becoming positive and T is said to be forward biased.
 At wt=α, T is triggered and source voltage Vs appears across the load as Vo.
 At wt=π, Vs is zero and just after this instant, as Vs tends to reverse, freewheeling diode FD is
forward biased through the conducting SCR. As a result i o is immediately transferred from T to FD.
 At wt=π, T is subjected to reverse voltage and zero current so T is turned off. It is assumed that
the load current does not decay to zero during freewheeling period until SCR is triggered again at
(2π+α).
 During the freewheeling period, output voltage Vo is zero.
ADVANTAGES OF USING FREEWHEELING DIODE
 Input power factor is improved.
 Load current waveform is improved and thus the load performance is better.

MAIN FUNCTIONS OF FREEWHEELING DIODE

 It prevents reversal of load voltage except for small diode voltage drop.
 I transfers the load current away from the rectifier, thereby allowing all of its thyristors to
regain their blocking states.

SINGLE PHASE HALF WAVE CONTROLLED RECTIFIER WITH RLE LOAD

 Minimum value of firing angle θ1= sin-1(E/Vm)
Maximum value of firing angle θ2=π-θ1
 During positive half cycle
T is fired at an angle α>θ1.
At α= 0 to θ1, as the thyristor is reverse biased, load current io is zero and load voltage Vo=E.
At wt=α, T is triggered and comes to on state. The load voltage follows the source voltage and i o
increases.
At wt=π, Vo=0 and io=0.
At wt=β
Due to inductance in the load, the load current io reaches to zero at wt=β. The
load voltage goes to negative and reaches to zero at wt=β.
At wt=β, io=0, then T is turned off automatically.
 During negative half cycle
T is reverse biased.
During the period β to 2π+α, io is zero but Vo= E.
TWO PULSE CONVERTERS
SINGLE PHASE FULLY CONTROLLED BRIDGE RECTIFIER WITH R LOAD

 During positive half cycle

T1, T2 are forward biased and they are triggered simultaneously.
At wt=α, T1, T2 are conducting, then current flows through the path P-T1-R-T2-N.
At wt=π, Vs falls to zero and current also goes to zero. Hence T1, T2 are turned off.
 During negative half cycle
T3, T4 are forward bias and they are triggered simultaneously.
At wt=π+α, T3, T4 are conducting, then current flows through the path N-T3-R-T4-P.
At wt= 2π, Supply voltage Vs and current goes to zero and T3, T4 are turned off.
 The output voltage can be varied by varying the firing angle α.
 So, the load current is always discontinuous with purely resistive load.
 By using full converter with R load, the output voltage and output current is always positive.
 A fully controlled rectifier with R load acts as a one quadrant converter.
13
SINGLE PHASE FULLY CONTROLLED BRIDGE RECTIFIER WITH RL LOAD

Single phase fully controlled bridge rectifier with RL load-Rectification mode (α< 90º)
14
Single phase fully controlled bridge rectifier with RL load- Inversion mode (α>90º)

 At firing angle wt=α (30º)

 T1, T2 are triggered. Current flows through the path P-T1-RL-T2-N.
 Supply voltage appears across the load and forces the current through the load. This load current
io is assumed to be continuous. The load current flows from source to load which is taken as
positive.
 At firing angle wt=π
 Source voltage reverses, but due to the very large inductance , the current is maintained in the same
direction at constant magnitude I which keeps T1, T2 in conducting state and hence negative
supply voltage appears across the load.
 At firing angle wt=π+α

15
  T3, T4 are triggered and with this, the negative line voltage reverse biases T1, T2 and T1, T2
are commutated. The current path is N-T3-RL-T4-P.

MODE-I: Rectification mode (α< 90º)

 During the interval α to π, both Vs and Is are positive. Therefore power flows from AC source
to load.
 During the interval π to π+α, both Vs is negative and Is is positive. Therefore the load returns some
of its energy to the supply system.
MODE-II: Inversion Mode
(α>90º)
 The firing pulses are retarded for 120º i.e., α=120º
 The output voltage waveform now contains a mean negative component. Also from the
Vdc equation, if α>90º, the voltage at the load terminal is negative, therefore the power flows from
DC side to AC side and the converter operates as a line commutated inverter. In this mode the
power flows from load to source.

16
 SINGLE PHASE FULLY CONTROLLED BRIDGE RECTIFIER WITH RLE LOAD
 At wt=α, T1, T2 are triggered and they conduct from wt=α to π+α. The conduction period of
the thyristors is 180º or π radians.
 At wt=π+α, forward biased thyristors T3, T4 are triggered. The supply voltage turns off T1, T2
by
line or natural commutation and the load current is transferred from T1, T2 to T3, T4. T3, T4 conduct
from wt=π+α to 2π+α.
 During wt=α to π, both Vs and Is is positive. Therefore power flows from AC source to load.
 During wt=π to π+α, Vs is negative but Is is positive. Therefore power flows from load to source.

Rectification mode
17
RLE Inversion Mode ( α>90º)

18
SINGLE PHASE SEMI CONVERTER
SINGLE PHASE HALF CONTROLLED BRIDGE RECTIFIER WITH R LOAD

 During positive half supply of the AC supply, T1 and D1 are forward biased. When T1 is triggered at
a firing angle wt=α, T1 and D1 come to on state. Now the load current path is P-T1-R-D1-N. During
this period we get positive output voltage and current.
 During negative half cycle of the AC supply, T2 and D2 is forward biased. When T2 is triggered at
firing angle wt=π+α, t2 and D2 come to on state. The load current path is N-T2-R-D2-P. During this
period we get positive output voltage and current.

19
SINGLE PHASE HALF CONTROLLED BRIDGE RECTIFIER WITH RL LOAD
 During positive half cycle (0 to π)
 T1, D1 are forward biased. At wt=α, T1, D1 comes to on state. Now the current path is P-T1-
RL- D2-N.
 During this period, output voltage will be zero because of closed current path.

 During negative half cycle

 At the instant (π+α), a triggering pulse is applied to the forward biased SCR T2.
 T2 is turned on. The supply voltage reverse biases T1 and T1 is turned off by natural
commutation.
 During this period output current is positive and output voltage is zero due to the closed circuit.

20
SINGLE PHASE HALF CONTROLLED RECTIFIER WITH RLE LOAD AND
FREEWHEELING DIODE

 After wt=0, T1 is forward biased, only when source voltage Vm sinwt exceeds E. Thus T1
is triggered at firing angle wt=α such that Vm sinα>E.
 At w=α, T1, D1 comes to the on state.
 During that period, we can get positive output voltage and current.
 During the period, π to π+α, the input voltage is negative and freewheeling diode FD is
forward biased.
 During that period, we can get zero output voltage and positive output current.

21
22
THREEPULSE CONVERTERS
THREE PHASE HALF CONTROLLED BRIDGE RECTIFIER
Mode 1: Continuous conduction mode

 At instant (π/3+ α), T1 is triggered with a firing angle α<60º. Since R-Y has the highest value
compared to other phases, T1 becomes on. The current path is R-T1-R-L-D3-Y.
 Then, phase R-B has the maximum value. Therefore, the current path shifts from Y to B, i.e,
T1 continues to conduct but current changes from D3 to D1. Therefore T1 conducts for 120º,
which is the maximum conduction period of the SCRs.
 For α<60º, the output voltage will never become negative. The output voltage waveforms
repeat
for every 120º.
Mode 2: Dis Continuous conduction mode
 This mode occurs for firing angles α>60º. The output voltage becomes zero because of
the freewheeling action. Freewheeling period is (α-π/3). Therfore input current flows for the
period (π-α) in each half cycle.
 When α increases, the duration of input current pulse decreases and the harmonic content in
the source current increases.

23
Fig. 4.2 Continuous conduction mode

24
 Dis Continuous conduction mode
SIX PULSE CONVERTER
ADVANTAGES
 Commutation is made very simple
 Distortion on the input side is reduced due to reduction in lower order harmonics.
 Inductance required in series is considerably decreased.

25
THREE PHASE FULLY CONTROLLED BRIDGE RECTIFIER

26
27
  Here, T1, T3, T5 forms a positive group, whereas T2, T4, T6 forms a negative group. The positive
group thyristors are turned on when the supply voltage is positive and negative group of thyristors
are turned on when the supply voltage is negative.
The line voltages are
Vry, Vrb, Vyb, Vyr, etc.
 The subscripts in sequence appear twice. When first subscript appears twice, the SCR in
the positive group pertaining to that line conducts for 120º.
 When second subscript comes twice, the SCR in the negative group pertaining to that line conducts
for 120º.
 From this wave form the output voltage is negative. This means DC source is delivering power
to AC source. This operation is called line commutated inverter operation.
 For α=0º to 90º, the converter operates in rectification mode and 90º to 180º, the converter
operates in inversion mode.

EFFECT OF SOURCE IMPEDENCE ON THE PERFORMANCE OF CONVERTER

EFFECTS OF SOURCE INDUCTANCE
 It lowers the mean output voltage
 It distorts the output voltage and current waveforms
 It modifies the performance of the converter
SINGLE PHASE FULL CONVERTER

 When terminal 1 of source voltage Vs is positive, current i1 flows through Ls, T1, load and
T2. This is shown in fig.b. i.e., L, T1, T2 and load.
 Similarly when terminal 2 of Vs is positive, load current i2 flows through T3, load and T4 and
this is shown as V2, Ls, T3, T4 and load.
 Because of the presence of source inductance Ls, the current through outgoing thyristors T3,
T4 decreases gradually to zero from its initial value of Io; whereas in incoming thyristors T1,
T2, the current builds up gradually from zero to full value of load current Io.

28
THREE PHASE FULL CONVERTER

29
  At wt=30º, T5 is outgoing SCR and T1 is incoming SCR and both T5, T1 belong to positive
group.
 As T1 is triggered, current through T5 starts decaying while through T1 current begins to build
up.
conduct.
 After wt=30+µ; T6, T1 conduct.
 At wt=90º, as T2 is triggered, I6 begins to decrease and I2 starts building up. Therefore
from wt=90º to 90º+µ, three SCRs T6, T1, T2 conduct.
 At wt=90º+µ, I6=0, I2=Io. After wt=90º+µ, only two SCRs T1, T2 conduct. This sequence
of operation repeats with other SCRs of the full converter.
DUAL CONVERTERS
 A full converter operates as a rectifier in first quadrant ( Vo,Io positive) from α=0º to 90º and as
an inverter (Vo negative Io positive) from α=90º to 180º in the fourth quadrant.
 In the first quadrant, power flows from AC source to the DC load and in the fourth quadrant, power
flows from DC circuit to the AC source.
 Four quadrant operation without any mechanical switchover can be achieved by connecting two
full converters. Such an arrangement using two full converters in antiparallel and connecting to
the same DC load is called a dual converter

30
  There are two functional modes of dual converter, one is non circulating current mode and
the other is circulating- current mode. Here, we use non- circulating type of dual converters in
single phase and three phase.
 Converter 1 operates in first and fourth quadrant and the second converter operates in second
and third quadrant.
 Thus a dual converter using two full converters can give four quadrant operation.

PRACTICAL DUAL CONVERTER

a. Dual converter without circulating current

31
 In this converter, only one con converter is in operation and it alone carries the
entire load current.
 Only, this converter receives the triggering pulse and the triggering pulse to the other
converter is removed.
 If suppose, the converter 1 is in operation and the converter 2 must be turned on, then
first the firing pulse to the converter 1 should be removed so that its load current will
decay to zero and
converter 1 will be made to conduct.
 Now the current in converter 2 will build up through the load in the reverse direction.
 As firing pulses are withdrawn from converter1, it is idle as long as the converter
2 is in operation.
 It should be ensured that during changeover from one converter to another converter,
the load current must decay to zero.
 After the outgoing converter stopped working, a delay time of 10 to 20 m sec is
introduced before applying firing pulses to the incoming converter.
 This time delay ensures the reliable commutation of SCRs in the outgoing converter.
 If the incoming converter is triggered, before completely turning off the outgoing
converter, then the circulating current will flow between the converters.
 With non-circulating current mode of dual converter, the load current may be continuous
or discontinuous.

32
Disadvantages
1. A reactor is required to limit the circulating current. The size and cost of this reactor may be
quite significant at higher power levels.
2. Circulating current causes more losses in the converters, hence the efficiency and
power factor are low. As the converters have to handle load as well as circulating
currents, the thyristors for two converters are rated for higher currents.

33
.

34
 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

2.5 UNI JUNCTION TRANSISTOR (UJT)

Unijunction transistor (abbreviated as UJT), also called the double-base diode is a 2-
layer, 3-terminal solid-state (silicon) switching device. The device has-a unique
characteristic that when it is triggered, its emitter current increases re generatively (due
to negative resistance characteristic) until it is restricted by emitter power supply.
Since the device has one p n junction and three leads p n junction and three leads

Figure 2.5.1 UJT structure, Equivalent circuit and Symbol

[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 105]

Construction of a UJT
The basic structure of a unijunction transistor is shown in figure. It essentially consists
of a lightly-doped N-type silicon bar with a small piece of heavily doped P-type
material alloyed to its one side to produce single P-N junction. The single P-N junction
accounts for the terminology unijunction. The silicon bar, at its ends, has two ohmic
contacts designated as base-1 (B1) and base- 2 (B2), as shown and the P-type region is
termed the emitter (E). The emitter junction is usually located closer to base-2 (B2)
than base-1 (B1) so that the device is not symmetrical, because symmetrical unit does
not provide optimum electrical characteristics for most of the applications.

The symbol for unijunction transistor is shown in figure. The emitter leg is drawn
at an angle to the vertical line representing the N-type material slab and the arrowhead
points in the direction of conventional current when the device is forward-biased,
active or in the conducting state. The basic arrangement for the UJT is shown in figure.
A complementary UJT is formed by diffusing an N-type emitter terminal on a P-type

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

base. Except for the polarities of voltage and current, the characteristics of a
complementary UJT are exactly the same as those of a conventional UJT.
 The device has only one junction, so it is called the unijunction device.

 The device, because of one P-N junction, is quite similar to a diode but it
differs from an ordinary diode as it has three terminals.

 The structure of a UJT is quite similar to that of an N-channel JFET. The

main difference is that P-type (gate) material surrounds the N-type (channel)
material in case of JFET and the gate surface of the JFET is much larger than
emitter junction of UJT.
 In a unijunction transistor the emitter is heavily doped while the N-region is
lightly doped, so the resistance between the base terminals is relatively high,
typically 4 to 10 kilo Ohm when the emitter is open.
 The N-type silicon bar has a high resistance and the resistance between
emitter and base-1 is larger than that between emitter and base-2. It is because
emitter is closer to base-2 than base-1.
 UJT is operated with emitter junction forward- biased while the JFET is
normally operated with the gate junction reverse-biased.
 UJT does not have ability to amplify but it has the ability to control a large ac
power with a small signal. It exhibits a negative resistance characteristic and
so it can be employed as an oscillator.
Operation of a UJT

Imagine that the emitter supply voltage is turned down to zero. Then the intrinsic
stand-off voltage reverse-biases the emitter diode, as mentioned above. If VB is the
barrier voltage of the emitter diode, then the total reverse bias voltage is VA + VB = η
VBB + VB. For silicon VB = 0.7 V. Now let the emitter supply voltage VE be slowly
increased. When VE becomes equal to η VBB, IEo will be reduced to zero. With equal
voltage levels on each side of the diode, neither reverse nor forward current will flow

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

Figure 2.5.2 operation UJT under (i) VE=0 (ii) applied VE

[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 105]

Figure 2.5.3 Equivalent circuit of UJT

[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 106]

When emitter supply voltage is further increased, the diode becomes forward-biased
as soon as it exceeds the total reverse bias voltage (η VBB + VB). This value of
emitter voltage VE is called the peak-point voltage and is denoted by VP. When VE =
VP, emitter current IE starts to flow through RB1 to ground, that is B1. This is the
minimum current that is required to trigger the UJT. This is called the peak-point
emitter current and denoted by IP. Ip is inversely proportional to the inter base voltage,
VBB.

Now when the emitter diode starts conducting, charge carriers are injected into the RB
region of the bar. Since the resistance of a semiconductor material depends upon
doping, the resistance of region RB decreases rapidly due to additional charge carriers
(holes). With this decrease in resistance, the voltage drop across RB also decrease,

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

because the emitter diode to be more heavily forward biased. This, in turn, results in
larger forward current, and consequently more charge carriers are injected causing still
further reduction in the resistance of the RB region. Thus the emitter current goes on
increasing until it is limited by the emitter power supply. Since VA decreases with the
increase in emitter current, the UJT is said to have negative resistance characteristic. It
is seen that the base-2 (B2) is used only for applying external voltage VBB across it.
Terminals E and B1 are the active terminals. UJT is usually triggered into conduction
by applying a suitable positive pulse to the emitter. It can be turned off by applying a
negative trigger pulse.
UJT Characteristics

Figure 2.5.4 Static Emitter Characteristic for a UJT

[Source: “Electronic devices and circuits” by “Balbir Kumar, Shail.B.Jain, and Page: 106]

The static emitter characteristic (a curve showing the relation between emitter voltage
VE and emitter current IE) of a UJT at a given inter base voltage VBB is shown in
figure. From figure it is noted that for emitter potentials to the left of peak point,
emitter current IE never exceeds IEo. The current IEo corresponds very closely to the
reverse leakage current ICo of the conventional BJT. This region, as shown in the
figure, is called the cut-off region. Once conduction is established at VE = VP the
emitter potential VE starts decreasing with the increase in emitter current IE. This
Corresponds exactly with the decrease in resistance RB for increasing current IE. This
device, therefore, has a negative resistance region which is stable enough to be used
with a great deal of reliability in the areas of applications listed earlier. Eventually, the

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 ROHINI COLLEGE OF ENGINEERING & TECHNOLOGY

valley point reaches, and any further increase in emitter current IE places the device
in the saturation region, as shown in the figure 2.5.4.
Three other important parameters for the UJT are IP, VV and IV and are defined
below:
Peak-Point Emitter Current Ip: It is the emitter current at the peak point. It
represents the minimum current that is required to trigger the device (UJT). It is
inversely proportional to the inter base voltage VBB.
Valley Point Voltage V: The valley point voltage is the emitter voltage at the valley
point. The valley voltage increases with the increase in inter base voltage VBB.
Valley Point Current IV: The valley point current is the emitter current at the valley
point. It increases with the increase in inter-base voltage VBB.
Special Features of UJT.
The special features of a UJT are:
1. A stable triggering voltage (VP) — a fixed fraction of applied inter base

voltage VBB.
2. A very low value of triggering current.

3. A high pulse current capability.

4. A negative resistance characteristic.

5. Low cost.

Applications of UJT.
 Relaxation oscillators.

 Switching Thyristors like SCR, TRIAC etc.

 Magnetic flux sensors.

 Voltage or current limiting circuit.

 Bistable oscillators.

 Voltage or current regulators.

 Phase control circuits.

EC8353 ELECTRONICS DEVICES AND CIRCUITS

 RELAXATION OSCILLATOR

The pulse signal required to drive the digital circuits can be obtained from a single
stage oscillator circuits using a particular device like unijunction transistor.

Such a oscillator which uses UJT is called UJT relaxation oscillator. The basic circuit
of UJT relaxation oscillator is shown in the Fig.

The R1 and R2 are biasing resistances which are selected such that they are lower
than interbase resistances RB1 and RB2.

The resistance RT and the capacitance CT decide the oscillating rate. The value of
RT is so selected that the operating point of UJT remains in the negative
resistance region.

The UJT characteristics and the negative resistance region of the characteristics
are shown in the Fig. The characteristics of UJT show the variation between V and
I where VE is emitter voltage and IE is emitter current.
OPERATION

Capacitor CT gets charged through the resistance RT towards supply voltage VBB
As long as the capacitor voltage is less than peak voltage Vp the emitter appears
as an open circuit.

When the capacitor voltage Vc exceeds the voltage Vp the UJT fires. The capacitor
starts discharging through R1 +RB1 where RB1 internal base resistance. As RB1 is
assumed negligible and hence capacitor discharges through R1.

Due to the design of R1 this discharge is very fast, and it produces a pulse across
R1 When the capacitor voltage falls below Vv i.e. VC = VE= VV the UJT gets turned
OFF. The capacitor starts charging again.

The discharge time of the pulse is controlled by the time constant CTR1 while the
charging time constant by RTCT.
 There is voltage drop across R2 and voltage rise across R1, when UJT fires. The
charging equation of the capacitor is given by,

Source : http://mediatoget.blogspot.in/2011/10/relaxation-oscillator.html
Lecture 01 The Operational Amplifier (Op-Amp)

The Operational Amplifier (Op-Amp)

1.1 General Concepts:

An operational amplifier, or op-amp, is a very high gain (A ≈ ∞) differential amplifier
with high input impedance (Zi ≈ ∞) and low output impedance (Zo ≈ 0). Typical uses of
the operational amplifier are to provide voltage amplitude changes (amplitude and
polarity), oscillators, filter circuits, and many types of instrumentation circuits. An op-amp
contains a number of differential amplifier stages to achieve a very high voltage gain.
The standard operational amplifier symbol is shown in Fig. 1-1(a). It has two input
terminals, the inverting (−) input and the noninverting (+) input, and one output terminal.
Each input results in either the same or an opposite polarity (or phase) output, depending
on whether the signal is applied to the plus (+) or the minus (−) input.
The typical op-amp operates with two dc supply voltages, one positive and the
other negative, as shown in Fig. 1-1(b). Usually these dc voltage terminals are left off the
schematic symbol for simplicity but are understood to be there.

(a) (b)
Fig. 1-1

1.2 Block Diagram and Differential Amplifier of an Op-Amp:

A typical op-amp is made up of three types of amplifier circuit: a differential amplifier, a
voltage amplifier, and a push-pull amplifier, as shown in Fig. 1-2. A differential amplifier
is the input stage for the op-amp, It provides amplification of the difference voltage
between the two inputs. The second stage is usually a class A amplifier that provides
additional gain. Some op-amps may have more than one voltage amplifier stage. A push-
pull class B amplifier is typically used for the output stage.

Fig. 1-2
1
Lecture 01 The Operational Amplifier (Op-Amp)

A differential amplifier forms the input stage of operational amplifiers. The term
differential comes from the amplifier's ability to amplify the difference of two input
signals applied to its inputs. Only the difference in the two signals is amplified; if there is
no difference, the output is zero. A basic differential amplifier circuit and its symbol are
shown in Fig. 1-3. The transistors (Q1 and Q2) and the collector resistors (RC1 and RC2) are
carefully matched to have identical characteristics. Notice that the two transistors share a
single emitter resistor, RE.

(a) (b)
Fig. 1-3

1.3 Op-Amp Operation Modes:

The differential amplifier exhibits three modes of operation based on the type of input
(and/or output) signals. These modes are single-ended, double-ended or differential, and
common. Since the differential amplifier is the input stage of the op-amp, the op-amp
exhibits the same modes.

Single-Ended Input: Single-ended input operation results when the input signal is
connected to one input with the other input connected to ground. Fig. 1-4 shows the
signals connected for this operation. In Fig. 1-4(a), the input is applied to the plus input
(with minus input at ground), which results in an output having the same polarity as the
applied input signal. Fig. 1-4(b) shows an input signal applied to the minus input, the
output then being opposite in phase to the applied signal.

(a) (b)
Fig. 1-4

2
Lecture 01 The Operational Amplifier (Op-Amp)

Double-Ended (Differential) Input: In addition to using only one input, it is

possible to apply signals at each input-this being a double-ended operation. Fig. 1-5(a)
shows an input, Vd, applied between the two input terminals (recall that neither input is at
ground), with the resulting amplified output in phase with that applied between the plus
and minus inputs. Fig. 1.5(b) shows the same action resulting when two separate signals
are applied to the inputs, the difference signal being Vi1 − Vi2.

(a) (b)
Fig. 1-5

Double-Ended Output: While the operation discussed so far had a single output, the
op-amp can also be operated with opposite outputs, as shown in Fig. 1-6(a). An input
applied to either input will result in outputs from both output terminals, these outputs
always being opposite in polarity. Fig. 1-6(b) shows a single-ended input with a double-
ended output. As shown, the signal applied to the plus input results in two amplified
outputs of opposite polarity. Fig. 1-6(c) shows the same operation with a single output
measured between output terminals (not with respect to ground). This difference output
signal is Vo1 − Vo2. The difference output is also referred to as a floating signal since
neither output terminal is the ground (reference) terminal. Notice that the difference output
is twice as large as either Vo1 or Vo2 since they are of opposite polarity and subtracting
them results in twice their amplitude. Fig. 1-6(d) shows a differential input, differential
output operation. The input is applied between the two input terminals and the output
taken from between the two output terminals. This is fully differential operation.

(a) (b)

(c) (d)
Fig. 1-6

3
Lecture 01 The Operational Amplifier (Op-Amp)

Common-Mode Operation: When the same input signals are applied to both inputs,
common-mode operation results, as shown in Fig. 1-7. Ideally, the two inputs are equally
amplified, and since they result in opposite polarity signals at the output, these signals
cancel, resulting in 0-V output. Practically, a small output signal will result.

Fig. 1-7

Common-Mode Rejection: A significant feature of a differential connection is that

the signals which are opposite at the inputs are highly amplified, while those which are
common to the two inputs are only slightly amplified-the overall operation being to
amplify the difference signal while rejecting the common signal at the two inputs. Since
noise (any unwanted input signal) is generally common to both inputs, the differential
connection tends to provide attenuation of this unwanted input while providing an
amplified output of the difference signal applied to the inputs. This operating feature,
referred to as common-mode rejection.

1.4 Common-Mode Reject Ratio (CMRR):

One of the more important features of a differential circuit connection, as provided in an
op-amp, is the circuit’s ability to greatly amplify signals that are opposite at the two
inputs, while only slightly amplifying signals that are common to both inputs. An op-amp
provides an output component that is due to the amplification of the difference of the
signals applied to the plus and minus inputs and a component due to the signals common
to both inputs. Since amplification of the opposite input signals is much greater than that
of the common input signals, the circuit provides a common mode rejection as described
by a numerical value called the common-mode rejection ratio (CMRR).

Differential Inputs: When separate inputs are applied to the op-amp, the resulting
difference signal is the difference between the two inputs.
= − [1-1]

Common Inputs: When both input signals are the same, a common signal element
due to the two inputs can be defined as the average of the sum of the two signals.
= ( + ) [1-2]

Output Voltage: Since any signals applied to an op-amp in general have both
in-phase and out-of phase components, the resulting output can be expressed as
= + [1-3]
where Ad = differential gain, and Ac = common-mode gain of the amplifier.

4
Lecture 01 The Operational Amplifier (Op-Amp)

Having obtained Ad and Ac, we can now calculate a value for the common-mode
rejection ratio (CMRR), which is defined by the following equation:
CMRR = [1-4]
The value of CMRR can also be expressed in logarithmic terms as
CMRR (dB) = 20 log [1-5]

Exercise 1-1:
Calculate the CMRR and express it in decibel for the circuit measurements shown in
Fig. 1-8.
[Answers: 666.7, 56.48 dB]

Fig. 1-8

Exercise 1-2:
Determine the output voltage of an op-amp for input voltages of Vi1 = 150 µV,
Vi2 = 140 µV. The amplifier has a differential gain of Ad = 4000 and the value of CMRR
is: (a) 100, and (b) 105.
[Answers: (a) 45.8 mV, (b) 40.006 mV]

5
Lecture 01 The Operational Amplifier (Op-Amp)

1.5 The Inverting Op-Amp:

Consider the configuration shown in Fig. 1-9(a). In this very useful application of an
operational amplifier, the noninverting input is grounded, vin is connected through R1 to
the inverting input, and feedback resistor Rf is connected between the output and vi‾. Since
we are using the amplifier in an inverting mode, we denote the voltage gain by −A,
vin ≠ vi‾ , we define =− .
From Fig. 1-9(b); =( − )⁄ , = ( − )⁄ , = + ,
and = ∞ => = 0 => = ,
or ( − )⁄ =( − )⁄ or − = − ,
and =− , | | = ∞ => = 0 => =− or

=− [1-6]
In Eqn. [1-6] the gain is negative, signifying that the configuration is an inverting
amplifier, also the magnitude of vo/vin depends only on the ratio of the resistor values. The
gain vo/vin is a closed-loop gain of the amplifier, while A is called the open-loop gain.

(a) (b)
Fig. 1-9

Exercise 1-3:
Assuming that the operational amplifier in Fig. 1-10 is ideal, find
(a) the rms value of vo when vin is 1.5 V rms,
(b) the rms value of the current in the 25-kΩ resistor when vin is 1.5 V rms, and
(c) the output voltage when vin = − 0.6 V dc.
[Answers: (a) 8.25 V rms, (b) 60 µA rms, (c) 3.3 V dc]

Fig. 1-10
6
Lecture 01 The Operational Amplifier (Op-Amp)

1.6 The Noninverting Op-Amp:

Fig. 1-11(a) shows another useful application of an operational amplifier, called the
noninverting configuration. The input signal vin is connected directly to the noninverting
input and R1 is connected from the inverting input to ground. Under the ideal assumption
of infinite input impedance, no current flows into the inverting input, so i1 = if .
Thus, = and = ( − ) => = − ⁄ ,

| | = ∞ => ⁄ = 0 => = and = , where = =>

=1+ = [1-7]
Eqn. [1-7] shows that the closed-loop gain of the noninverting amplifier, like that of
the inverting amplifier, depends only on the values of external resistors. Fig. 1-11(b)
shows a special case of noninverting amplifier, used in applications where power gain and
impedance isolation are of primary concern. When Rf = 0 and R1 = ∞, so the closed-loop
gain is ⁄ = 1 + ⁄ = 1. This configuration is called a voltage follower because
vo has the same magnitude and phase as vin. It has large input impedance and small output
impedance, and is used as a buffer amplifier between a high-impedance source and a
low-impedance load.

(a) (b)
Fig. 1-11

Exercise 1-4:
In a certain application, a signal source having 60 kΩ of source impedance, RS, produces a
1-V-rms signal. This signal must be amplified to 2.5 V rms and drive a 1-kΩ load.
Assuming that the phase of the load voltage is of no concern, design an operational
amplifier circuit for the application.
Hint: Choose, arbitrarily, input resistor, R1 = 100 kΩ and find feedback resistor, Rf.
Since phase is of no concern and the required voltage gain is greater than 1, we can use
either an inverting or noninverting amplifier.
[Answers: Rf (inverting) = 400 kΩ, Rf (noninverting) = 150 kΩ]

7
Lecture 01 The Operational Amplifier (Op-Amp)

1.7 Op-Amp Analysis using Feedback Theory:

We have seen that we can control the closed-loop gain vo/vin of an operational amplifier by
introducing feedback through external resistor combinations. We wish now to examine the
feedback mechanism in detail and discover some other important consequences of its use.
Feedback theory is widely used to study the behavior of electronic components as well as
complex systems in many different technical fields, so it is important to develop an
appreciation and understanding of its underlying principles.

1.7.1 Feedback in the Noninverting Op-Amp:

Fig. 1-12 shows the noninverting configuration along with an equivalent block diagram on
which we can identify the signal and feedback paths. “A” represents the amplifier and its
open-loop gain, “β” is called the feedback ratio and represents the output voltage that is
fed back to the input. ve = vin – vf. ve is often called the error voltage. The feedback voltage
vf = βvo corresponds to vi‾ in the amplifier circuit. Since the feedback voltage subtracts
from the input voltage, the amplifier is said to have negative feedback.

(a)

(b)

Fig. 1-12

With reference to Fig. 1-12(b), we see that = − , = =>

= ( − )= − or (1 + )= =>
⁄
= = ⁄
[1-8]

Form a voltage divider across vo, = , = = =>

= (noninverting op-amp) [1-9]

8
Lecture 01 The Operational Amplifier (Op-Amp)

Substituting Eqn. [1-9] into Eqn. [1-8], we find

⁄ ⁄
= ⁄
= ⁄
[1-10]
when = ∞ =>
= = = 1+ [1-11]
Eqn. [1-11] is exactly the same result we obtained from Eqn. [1-7].
Negative feedback improves the performance of an amplifier in several ways. In the
case of the noninverting amplifier, it can be shown that the input resistance seen by the
signal source (looking directly into the + terminal) is
= = (1 + ) ≈ [1-12]
where rid is the differential input resistance of the amplifier.
The closed-loop output resistance of the noninverting amplifier is also improved by
negative feedback:
= ( )= ≈ [1-13]
where ro is the open-loop output resistance of the amplifier.

Exercise 1-5:
Find the closed-loop gain of the amplifier in Fig. 1-13 when (a) A = ∞, (b) A = 106, and
(c) A = 103.
[Answers: (a) 10, (b) 9.9990, (c) 9.90099]

Fig. 1-13

Exercise 1-6:
An operational amplifier has open-loop gain A = 104. Compare its closed-loop gain with
that of an ideal amplifier when (a) β = 0.1, and (b) β = 0.001.
[Answers: (a) 9.99, (b) 909.09]

Exercise 1-7:
A noninverting op-amp has open-loop gain A = 105, feedback ratio β = 0.01, differential
input resistance rid = 20 kΩ, and open-loop output resistance ro = 75 Ω. Find the closed-
loop input (rif) and output (rof) resistances of the amplifier.
[Answers: 20 MΩ, 0.075 Ω]

9
Lecture 01 The Operational Amplifier (Op-Amp)

1.7.2 Feedback in the Inverting Op-Amp:

To investigate the effect of open-loop gain A and feedback ratio β on the closed-loop gain
of the inverting amplifier, let us recall Fig. 1-9(b):
− = − and =− => + =− − or

+ + =− or 1+ =− =>
⁄
= ⁄
[1-14]
Once again, when A = ∞, we see that the closed-loop gain reduces to the ideal
amplifier value, −Rf/R1 (Eqn. [1-6]). By the superposition principle, we can analyze the
contribution of the feedback source by grounding all other signal sources. When this is
done, as shown in Fig. 1-14, we see that the feedback voltage in both configurations is
developed across R1 and Rf by voltage divider, and β = R1/(R1+Rf) in both cases. In view
of this fact, we can write Eqn. [1-14] as
⁄
= ⁄
[1-15]

Fig. 1-14

Towards developing a feedback model for the inverting amplifier, consider the
block diagram shown in Fig. 1-15. It is quite similar to Fig. 1-12(b) for the noninverting
amplifier, except that we now denote the open loop gain by –A, v represents an arbitrary
input voltage, rather than vin. As shown in the figure;
⁄ ⁄
=− ( + ) or = = ⁄
=> = ⁄
.
Multiplying the right side by the factor ⁄( + ) , we would obtain
⁄
= ⁄
= ⁄
[1-16]

10
Lecture 01 The Operational Amplifier (Op-Amp)

Fig. 1-15

Eqn. [1-16] gives us exactly the same result (Eqn. [1-15] with vin = v) that we obtain
for the inverting amplifier. Therefore, we modify the block-diagram model in Fig. 1-15 by
adding a block that multiplies the input by ⁄( + ). The complete feedback model is
shown in Fig. 1-16. As can be seen, the loop gain for the inverting amplifier is Aβ, the
same as that for the noninverting amplifier.

Fig. 1-16

It can be shown that the input resistance seen by the signal source driving the
inverting amplifier is
= = + ≈ [1-17]
As with the noninverting amplifier, the output resistance of the inverting amplifier is
decreased by the negative feedback. In fact, the relationship between output resistance and
loop gain is the same for both:
= ( )= ≈ [1-18]

11
Lecture 01 The Operational Amplifier (Op-Amp)

In closing our discussion of feedback theory, we should note once again that the
same relationship between actual and ideal closed-loop gain applies to inverting and
noninverting amplifiers. This relationship is
= ⁄
[1-19]
where (ideal closed-loop gain) is the closed-loop gain vo/vin that would result if the
amplifier were ideal (A = ∞). We saw this relationship in Eqn. 1-10 and Eqn. 1-15,
repeated here:
⁄
= ⁄
(noninverting op-amp)
⁄
= ⁄
(inverting op-amp)
In both cases, the numerator is the closed-loop gain that would result if the amplifier
were ideal. Also in both cases, the greater the value of the loop gain Aβ, the closer the
actual closed-loop gain is to the ideal closed-loop gain.

Exercise 1-8:
The amplifier shown in Fig. 1-17 has open-loop gain equal to −2500 and open-loop output
resistance 100Ω. Find
(a) the magnitude of the loop gain (Aβ),
(b) the closed-loop gain (vo/vin),
(c) the input resistance (rif) seen by vin, and
(d) the closed-loop output resistance (rof).
[Answers: (a) 24.75, (b) − 96.12 (≈ − 100), (c) 1560 Ω, (d) 3.88 Ω]

Fig. 1-17

1.8 Frequency Response and Stability:

When the word stability is used in high-gain amplifier, it means behaving like an amplifier
rather than like an oscillator. an operational amplifier has very high gain, so precautions
must be taken in its design to ensure that it does not oscillate (an oscillator is a device that
generates an ac signal because of positive feedback), large gains at high frequencies tend
to make an amplifier unstable, to ensure stable operation, most operational amplifiers have
internal compensation circuitry that causes the open-loop gain to diminish with increasing
frequency. This reduction in gain is called rolling-off the amplifier. The usable frequency
range rolls off at the rate of − 20 dB/decade, or − 6 dB/octave.

12
Lecture 01 The Operational Amplifier (Op-Amp)

1.9 The Gain-Bandwidth Product:

Fig. 1-18 shows frequency response characteristic for the open-loop gain of an operational
amplifier, fc is the cutoff frequency (the frequency at which the gain A falls to √2⁄2 times
its low-frequency or dc value, Ao). The slope of the single-pole response, − 20 dB/decade,
is −1. The frequency at which the β falls to the value 1 (unity) is given by fT = βmfβ, where
βm is the low frequency β (or hfe) and fB is the β cutoff frequency. Using exactly the same
approach;
= [1-20]
where ft = the unity-gain frequency, the frequency at which the gain equals 1, Ao = the
low-frequency, or dc, value of the open-loop gain, and fc = the cutoff frequency, or 3-dB
frequency, of the open-loop gain.
Since the amplifier is dc (lower cutoff frequency = 0), the bandwidth equals fc. The
term Aofc in Eqn. [1-20] is called the gain-bandwidth product or for its equivalent, the
unity-gain frequency.
The relationship between closed-loop bandwidth (BWCL) and the gain-bandwidth
product is closely approximated by
= = [1-21]
where β is the feedback ratio.

Fig. 1-18

Exercise 1-9:
Each of the amplifiers shown in Fig. 1-19 has an open-loop, gain-bandwidth product equal
to 1 × 106. Find the cutoff frequencies in the closed-loop configurations shown.
[Answers: (a) 40 kHz, (b) 400 kHz]

(a) (b)
Fig. 1-19

13
Lecture 01 The Operational Amplifier (Op-Amp)

Exercise 1-10:
With reference to the amplifier whose frequency response is shown in Fig 1-20, find
(a) the unity-gain frequency,
(b) the gain-bandwidth product,
(c) the bandwidth when the feedback ratio is 0.02, and
(d) the closed-loop gain at 0.4 MHz when the feedback ratio is 0.04.
[Answers: (a) 1 MHz, (b) 106, (c) 20 kHz, (d) 2.5]

Fig. 1-20

1.10 Slew Rate:

As mentioned previously, the internal compensation circuitry used to ensure amplifier
stability also affects the frequency response and places a limit on the maximum operating
frequency. The capacitor(s) in this compensation circuitry limit amplifier performance
because when the amplifier is driven by pulse-type signal, the capacitance must charge and
discharge rapidly in order for the output to keep up with the input. Since the voltage across
a capacitor cannot be changed instantaneously, there is an inherent limit on the rate at
which the output voltage can change. The maximum possible rate at which an amplifier's
output voltage can change, in volts per second, is called its slew rate.
It is not possible for any waveform, input or output, to change from one level to
another in zero time. An instantaneous change corresponds to an infinite rate of change,
which is not realizable in any physical system. Therefore, in our investigation of
performance limitations imposed by an amplifier’s slew rate, we need only concern
ourselves with inputs that undergo a total change in voltage, ΔV, over some nonzero time
interval, Δt. For simplicity, we will assume that the change is linear with respect to time,
that is, it is a ramp-type waveform, as illustrated in Fig. 1-21. The rate of change of this
kind of waveform is the change in voltage divided by the length of time that it takes for the
change to occur:
∆
ℎ = = volts/seconds [1-22]
∆
Since the value specified for the slew rate of an amplifier is the maximum rate at
which its output can change, we cannot drive the amplifier with any kind of input
waveform that would require the output to exceed that rate. Finally, the maximum
frequency at which an amplifier can be operated depends on both the bandwidth and the
slew rate.
14
Lecture 01 The Operational Amplifier (Op-Amp)

Fig. 1-21

Exercise 1-11:
The operational amplifier in Fig. 1-22 has a slew rate specification of 0.5 V/μs. If the input
is the ramp waveform shown, what is the maximum closed-loop gain that the amplifier can
have without exceeding its slew rate? determine the output levels corresponding to the
input levels and verify the specified slew rate.
[Answers: 12.5, +2.5 V/–7.5 V, 0.5 V/µs]

Fig. 1-22

1.11 Offset Currents and Voltages:

One of the characteristics of an ideal operational amplifier is that it has zero output voltage
when both inputs are 0 volts (grounded). This characteristic is particularly important in
applications where dc or low-frequency signals are involved. If the output is not 0 when
the inputs are 0, then the output will not be at its correct dc level when the input is a dc
level other than 0. The actual value of the output voltage when the inputs are 0 is called
the output offset voltage.
Manufacturers do not generally specify output offset because, the offset level
depends on the closed-loop gain that a user designs through choice of external component
values. Instead, input offsets are specified, and the designer can use these values to
compute the output offset that results in a particular application. Output offset voltages are
the result of two distinct input phenomena: input bias currents and input offset voltage.

15
Lecture 01 The Operational Amplifier (Op-Amp)

1.11.1 Input Offset Current:

We know that some dc base current (IB) must flow when a transistor is properly biased,
although its small its flowing through the external resistors produces a dc input voltage
that in turn creates an output offset. To reduce the effect of bias currents (IB+ and IB−),
a compensating resistor Rc, as shown in Fig. 1-23, is connected in series with the
noninverting (+) terminal of the amplifier (Rc provide a dc path to ground, so if a signal is
capacitor coupled to the + input, Rc must be connected between the + input and ground).
The proper choice of the value of Rc will minimize the output offset voltage due to bias
current. Fig. 1-24(a) shows the equivalent circuit of Fig. 1-23. Here, the bias currents are
represented by current sources having resistances R1 and Rc. Also, Fig. 1-24(b) shows the
same circuit when the current sources are replaced by their Thevenin equivalent voltage
sources.

Fig. 1-23

(a) (b)
Fig. 1-24

Using Fig. 1-24(b), we can apply the superposition principle to determine the output
offset voltage due to each input source acting alone and then combining the results:
= =− and = =>
( )= + = − [1-23]
= = => ( )= − = 0 =>
− = 0 => = ⁄

= = [1-24]

16
Lecture 01 The Operational Amplifier (Op-Amp)

Eqn. [1-24] reveals the very important result that output offset due to input bias currents
can be minimized by connecting a resistor Rc having value R1║Rf in series with the
noninverting input. We can compute the exact value of VOS(IB) when Rc = R1║Rf by
substituting this value of Rc back into Eqn. [1-23];
( )= ‖ − or

( )= − =>
( )=( − ) [1-25]
Eqn. [1-25] shows the offset voltage is proportional to the difference between IB and IB−
+

when Rc = R1║Rf. The equation confirms the fact that VOS = 0 if IB+ exactly equals IB−. The
quantity (IB+− IB−) is called the input offset current and is often quoted in manufacturers
specifications. Letting the input offset current (IB+− IB−) be designed by Iio, we have,
( )= when = ‖
VOS(IB) may be either positive or negative, depending on whether IB+ > IB− or vice versa,
so a more useful form is
| ( )| = | | when = ‖ [1-26]
Manufacturers specifications always give a positive value for Iio (absolute value). From
Eqn. [1-26] the output offset is directly proportional to Rf. For that reason, small resistance
values should be used when offset is a critical consideration. Another common
manufacturers specification is called input bias current, IB. By convention, IB is the average
of IB+ and IB−;
=
IB typically much larger than Iio because IB is on the same order of magnitude as IB+ and
IB−, while Iio is the difference between the two. Given values for IB and Iio, we can find IB+
and IB−, provided we know which is the larger:
= + 0.5| |
( > ) and
= − 0.5| |
= − 0.5| |
( < ) [1-27]
= + 0.5| |

Exercise 1-12:
Given = and | | = | − | , solve equations simultaneously to show that
(a) when > , = + 0.5| | and = − 0.5| |, and
(b) when < , = − 0.5| | and = + 0.5| |.
Hint: When > ,| − |= − .

17
Lecture 01 The Operational Amplifier (Op-Amp)

Exercise 1-13:
The specifications for the operational amplifier in Fig. 1-25 state that the input bias current
(IB) is 80 nA and that the input offset current (Iio) is 20 nA.
(a) Find the optimum value for Rc.
(b) Find the magnitude of the output offset voltage due to bias currents when Rc equals
its optimum value.
(c) Assuming that IB+ > IB−, find the magnitude of the output offset voltage when
Rc = 0.
[Answers: (a) 9.09 kΩ, (b) 2 mV, (c) 7 mV]

Fig. 1-25

1.11.2 Input Offset Voltage:

Another input phenomenon that contributes to output offset voltage is an internally
generated potential difference that exists because of imperfect matching of the input
transistors. This potential may be due to a difference between the VBE drops of the
transistors in the input differential stage of a BJT amplifier. Called input offset voltage,
the net effect of this potential difference is the same as if a small dc voltage source were
connected to one of the inputs (as shown in Fig. 1-26). The output offset voltage when the
input is Vio is given by
( )= = [1-28]

Fig. 1-26

18
Lecture 01 The Operational Amplifier (Op-Amp)

Exercise 1-14:
The specifications for the amplifier in Exercise 1-13 state that the input offset voltage is
0.8 m V. Find the output offset due to this input offset.
[Answer: 8.8 mV]

1.1.3 The Total Output Voltage:

We have seen that output offset voltage is a function of two distinct input characteristics:
input bias currents and input offset voltage. It is good design practice to assume a worst-
case situation, in which the two offsets have the same polarity and reinforce each other,
for the worst-case situation, we assume that the total offset is the sum of the respective
magnitudes:
| | = | ( )| + | ( )| (worst case) [1-29]

Exercise 1-15:
The operational amplifier in Fig. 1-27 has the following specifications: input bias current
(IB) = 100 nA; input offset current (Iio) = 20 nA; input offset voltage (Vio) = 0.5 mV. Find
the worst-case output offset voltage. Consider the two possibilities IB+ > IB− and vice
versa.
Hint: First check to see if the 10 kΩ resistor in series with the noninverting input
has the optimum value of a compensating resistor (RC).
[Answers: Rc is not optimum, IB+/− = 110/90 nA (vice versa),
VOS(IB) = −0.15/−2.85 mV, VOS(Vio) = 3 mV, VOS = 5.85 mV]

Exercise 1-16:
Assuming worst-case conditions at 25°C with the maximum value of input offset current
(Iio) = 200 nA and the maximum value of input offset voltage (Vio) = 5 mV, determine the
total output offset voltage │VOS│, in connection with the μA741 op-amp circuit shown in
Fig. 1-28.
Hint: Check the optimum value of a compensating resistor (RC).
[Answer: 90.1 mV]

Fig. 1-27 Fig. 1-28

19
Lecture 01 The Operational Amplifier (Op-Amp)

1.12 Typical Op-Amp Datasheet and Its Specifications:

20
Lecture 01 The Operational Amplifier (Op-Amp)

21
Lecture 02 Applications of Operational Amplifiers

Applications of Operational Amplifiers

2.1 Voltage Summation:

It is possible to scale a signal voltage, that is, to multiply it by a fixed constant, through an
appropriate choice of external resistors that determine the closed-loop gain of an amplifier
circuit. This operation can be accomplished in either an inverting or noninverting
configuration. It is also possible to sum several signal voltages in one operational-
amplifier circuit and at the same time scale each by a different factor. This called a linear
combination and the circuit that produces it is often called a linear-combination circuit as
shown in Fig. 2-1. For the three-input inverting amplifier of Fig. 2-1,
+ + = or + + =− =>

=− + + [2-1]
when = = = ;
=− ( + + ) [2-2]
when = ;
= −( + + ) [2-3]
The feedback ratio;
= [2-4]
where = ‖ ‖ .
The optimum value of the compensation resistor is
= =R ‖ ‖ ‖ [2-5]

Fig. 2-1

Fig. 2-2 shows a noninverting version of the linear-combination circuit. In this

example, only two inputs are connected and it can be shown that
= + [2-6]
Although this circuit does not invert the scaled sum, it is somewhat more cumbersome
than the inverting circuit, in applications where a noninverted sum is required, it can be
obtained using the inverting circuit of Fig. 2-1, followed by a unity-gain inverter.
1
Lecture 02 Applications of Operational Amplifiers

Fig. 2-2

Exercise 2-1:
(a) Design an operational-amplifier circuit that will produce an output equal to
−(4 + + 0.1 ). Use Rf = 60 kΩ.
(b) Write an expression for the output and sketch its waveform when =2 V,
= +5 V dc, and = −100 V dc.
[Answers: (a) R1 = 15 kΩ, R2 = 60 kΩ, R3 = 600 kΩ, Rc = 9.8 kΩ, Fig. 2-3(a)
(b) = 5 − 8 sin , Fig. 2-3(b)]

(a)

(b)

Fig. 2-3

2
Lecture 02 Applications of Operational Amplifiers

2.2 Voltage Subtraction:

Suppose we wish to produce an output voltage that equals the mathematical difference
between two input signals. This operation can be performed by using a differential mode,
where the signals are connected to the inverting and noninverting terminals. Fig. 2-4
shows the differential configuration. We can use the superposition principle to determine
the output of this circuit;
= and = = ,

so =− =>

= + = − [2-7]
If = = and = = =>
= + = − =>
= ( − ) [2-8]
where A is a fixed constant, the bias compensation resistance (Rc = R1||R2) is automatically
the correct value (R3||R4), namely R||AR.

Fig. 2-4

Let the general form of the output of Fig. 2-4 be

= − [2-9]
where = and = => = (1 + ) , but < 1,
to produce = − , we must have < (1 + ), this restriction limits the
usefulness of the circuit.
Moreover, we note that the compensation resistance (Rc = R1||R2) is not equal to its
optimum value R3||R4. With some algebraic complication, we can impose the additional
condition R1||R2 = R3||R4 and thereby force the compensation resistance to have its
optimum value. With = − , it can be shown that the compensation resistance
(Rc = R1||R2) is optimum when the resistor values are selected in accordance with;
= = = (1 + − ) [2-10]

3
Lecture 02 Applications of Operational Amplifiers

Although the circuit of Fig. 2-4 is a useful and economic way to obtain a difference
voltage of the form = ( − ), our analysis has shown that it has limitations and
complications when we want to produce an output of the general form = − .
An alternate way to obtain a scaled difference between two signal inputs is to use two
inverting amplifiers, as shown in Fig. 2-5.

Fig. 2-5

The output of the first amplifier is

=− ,
and the output of the second amplifier is
=− + = = − [2-11]
This equation shows that there is a great deal of flexibility in the choice of resistor values
necessary to obtain = − , since a large number of combinations will satisfy;
= and = .
Furthermore, there are no restrictions on the choice of values for a1 and a2, nor any
complications in setting Rc to its optimum value.

Exercise 2-2:
If the resistor values in Fig. 2-4 are chosen in according with
= = = (1 + − ), then,
assuming that < (1 + ), show that
(a) = − , and
(b) the compensation resistance (Rc = R1||R2) has its optimum value (R3||R4).

Exercise 2-3:
Design an operational-amplifier circuit using the differential configuration to produce the
output = 0.5 − 2.0 . Assume R4 = 100 kΩ. Check if the compensation resistance
has its optimum value.
[Answer: R1 = 200 kΩ, R2 = 40 kΩ, R3 = 50 kΩ, Rc = 9.8 kΩ,
Rc = R1||R2 = 33.3 kΩ = R3||R4 (as required)]
4
Lecture 02 Applications of Operational Amplifiers

Exercise 2-4:
Design an op-amp circuit to produce the output = 20 − 0.2 . First, check if you
can use the differential circuit.
[Answer: = 20 > (1 + ) = 1.2 (we cannot use the differential circuit),
Two of many design models are shown in Fig. 2-6(a) and (b)]

(a)

(b)

Fig. 2-6

Exercise 2-5:
(a) Design an operational-amplifier circuit using two inverting configurations to
produce the output = −10 + 5 + 0.5 − 20 . Choose feedback resistor
Rf = 100 kΩ for each amplifier.
(b) Assuming that the unity-gain frequency of each amplifier is 1 MHz, find the
approximate, overall, closed-loop bandwidth of your solution.
[Answers: (a) One of many possible solutions is shown in Fig. 2-7,
(b) BWCL(Overall) = Min. (BWCL1= 153.8 kHz, BWCL2= 31.2 kHz) = 31.2 kHz]

5
Lecture 02 Applications of Operational Amplifiers

Fig. 2-7

2.3 Controlled Voltage and Current Sources:

A controlled source is one whose output voltage or current is determined by magnitude of
another, independent voltage or current.

2.3.1 Voltage-Controlled Voltage Source (VCVS):

An ideal, voltage-controlled voltage source is one whose output voltage Vo equals a fixed
constant (k) times the value of another, controlling voltage: Vo = kVi; and is independent of
the current drawn from it. The constant k is dimensionless. Both the inverting and
noninverting configurations of an ideal operational amplifier meet the two criteria. In each
case, the output voltage equals a fixed constant (the closed-loop gain, determined by
external resistors) times an input voltage. Also, since the output resistance is (ideally) 0,
there is no voltage division at the output and the voltage is independent of load.

2.3.2 Voltage-Controlled Current Source (VCCS):

An ideal, voltage-controlled current source is one that supplies a current whose magnitude
equals a fixed constant (k) times the value of an independent controlling voltage: Io = kVi;
and is independent of the load to which the current is supplied. The constant k has the
dimensions of conductance (siemens). Since it relates output current to input voltage, it is
called the transconductance, gm, of the source. Fig. 2-8 shows two familiar amplifier
circuits: the inverting and noninverting configurations of an op-amp.
In Fig. 2-8(a), v− is virtual ground, so I1 = Vin/R1. Since no current flows into the
inverting terminal of the ideal amplifier, IL = I1, or
= ⁄ = [2-12]
The transconductance gm = 1/R1 siemens. Since RL does not appear in the equation, so the
load current is independent of load resistance. This version of a controlled current source
is said to have a floating load, because neither side of RL can be grounded.
In Fig. 2.8(b), v− = Vin, so I1 = Vin/R1. Once again, no current flows into the inverting
terminal, so IL = I1. Therefore, = ⁄ = . As in the inverting configuration,
the load current is independent of RL and the transconductance is 1/R1 siemens. The load is
also floating in this version.
6
Lecture 02 Applications of Operational Amplifiers

Of course, there is a practical limit on the range of load resistance RL that can be
used in each circuit. If RL, is made too large, the output voltage of the amplifier will
approach its maximum limit, as determined by the power supply voltages. For successful
operation, the load resistance in each circuit must obey
| |
< (inverting circuit)
| |
< −1 (noninverting circuit) [2-13]
where | | is the magnitude of the maximum output voltage of the amplifier.

(a) (b)
Fig. 2-8

Fig. 2-9 shows a voltage-controlled current source that can be operated with a
grounded load. Since there is (ideally) zero current into the + input, Kirchhoff's current
law at the node where RL is connected to the + input gives
= = = = and
= + = + = − + − =>
= ⁄ = [2-14]
This equation shows that the load current is controlled by Vin, and that it is independent of
RL. For successful operation, the load resistance must obey
| |
< [2-15]

Fig. 2-9
7
Lecture 02 Applications of Operational Amplifiers

Exercise 2-6:
Design an inverting, floating load, voltage-controlled current source that will supply a
constant current of 0.2 mA when the controlling voltage is 1 V. What is the maximum load
resistance for this supply if the maximum amplifier output voltage is 20 V?
[Answer: R1 = 1/gm = 5 kΩ, RL < 100 kΩ, Fig. 2-10]

Fig. 2-10

Exercise 2-7:
Find the current through each resistor and the voltage at each node of the voltage-
controlled current source in Fig. 2-11. What is the transconductance of the source?
[Answer: VA = 3.75 V, VB = 7.5 V, VC = 3.75 V, IL = 2.5 mA, I1 = 1.5625 mA,
I2 = 0.9375 mA, I3 = 0.9375 mA, I4 = 0.9375 mA, gm = 0.25 nS]

Fig. 2-11

2.3.3 Current-Controlled Voltage Source (CCVS):

An ideal current-controlled voltage source has an output voltage that is equal to a constant
(k) times the magnitude of an independent current: vo = kIi; and is independent of the load
connected to it. Here, the constant k has the units of ohms. A current controlled voltage
source can be thought of as a current-to-voltage converter, since output voltage is
proportional to input current. It is useful in applications where current measurements are
required, because it is generally more convenient to measure voltages.
Fig. 2-12 shows a very simple current-controlled voltage source. Since no current
flows into the − input, the controlling current Iin, is the same as the current in feedback
resistor R. Since v− is virtual ground,
8
Lecture 02 Applications of Operational Amplifiers

=− [2-16]
Once again, the fact that the amplifier has zero output resistance implies that the output
voltage will be independent of load.

Fig. 2-12

2.3.4 Current-Controlled Current Source (CCCS):

An ideal current-controlled current source is one that supplies a current whose magnitude
equals a fixed constant (k) times the values of an independent controlling current: Io = kIi;
and is independent of the load to which the current is supplied. The constant k is
dimensionless, since it is the ratio of two currents.
Fig. 2-13 shows a current-controlled current source with floating load RL. Since no
current flows into the − input, the current in R2 must equal Iin. Since v− is at virtual ground,
=− => = = and = + = + =>
= +1 [2-17]
This equation shows that the load current equals the constant (l + R2/R1) times the
controlling current and that IL is independent of RL. For successful operation, RL must obey
| |
< − [2-18]
The circuit of Fig. 2.13 may be regarded as a current amplifier, the amplification
factor being
= ⁄ = 1+ ⁄ [2-19]

Fig. 2-13
9
Lecture 02 Applications of Operational Amplifiers

Exercise 2-8:
It is desired to measure a dc current that ranges from 0 to 1 mA using an ammeter whose
most sensitive range is 0 to 10 mA. To improve the measurement accuracy, the current to
be measured should be amplified by a factor of 10.
(a) Design the circuit.
(b) Assuming that the meter resistance is 150 Ω and the maximum output voltage of the
amplifier is 15 V, verify that the circuit will perform properly.
[Answers: (a) Fig. 2-14, k = IL/IX = 1+ R2/R1 = 10 as required,
(b) Rmeter = 150 Ω < RL = 600 Ω]

Fig. 2-14

2.4 Op-Amp Integrators:

An electronic integrator is a device that produces an output waveform whose value at any
instant of time equals the total area under the input waveform up to that point in time.
A mathematical integration, the process produces the time varying function ∫ .
To illustrate this concept, suppose the input to an electronic integrator is the dc level E
volts, which is first connected to integrator at an instant of time we will call t = 0. Refer to
Fig. 2-15. The plot of the dc "waveform" versus time is simply a horizontal line at level E
volts, since the dc voltage is constant. The more time that we allow to pass, the greater the
area that accumulates under the dc waveform. At any time-point t, the total area under the
input waveform between time 0 and time t is (height) × (width) = Et, volts, as illustrated in
figure. For example, if E = 5 V dc, then the output will be 5 V at t = 1 s, 10 V at t = 2 s,
15 V at t = 3 s, and so forth. We see that the output is the ramp voltage v(t) = Et.

Fig. 2-15

10
Lecture 02 Applications of Operational Amplifiers

Fig. 2-16 shows how an electronic integrator is constructed using an operational

amplifier. The component in the feedback path is capacitor C, and the amplifier is operated
in an inverting configuration. To represent integration of the voltage v between time 0 and
time t, we are assuming zero input offset, the output of this circuit is
( )= ∫ [2-20]
This equation shows that the output is the (inverted) integral of the input, multiplied by the
constant l/R1C. If this circuit were used to integrate the dc waveform shown in Fig. 2-15,
the output would be a negative-going ramp (vo = −Et/R1C).

Fig. 2-16

Now we demonstrate why the circuit of Fig. 2-16 performs integration. Since the
current into the − input is 0, we have, from Kirchhoff's current law;
+ = 0,
where i1 is the input current through R1 and iC is the feedback current through the
capacitor. Since v− = 0, the current in the capacitor is
= => + = 0 or = .
Integrating both sides of the last equation with respect to t, we obtain
( )= ∫ .
It can be shown, using calculus, that the mathematical integral of the sine wave
A sin ωt is
∫( sin ) = sin( + 90) = cos( ).
Therefore, if the input to the inverting integrator in Fig. 2-16 is vin = A sin ωt, the output is
= ∫( sin ) = (−cos ) = cos [2-21]
The most important fact revealed by Eqn. [2-21] is that the output of an integrator with
sinusoidal input is a sinusoidal waveform whose amplitude is inversely proportional to its
frequency. This observation follows from the presence of ω (= 2πƒ) in the denominator of
Eqn. [2-21].
A gain magnitude is the ratio of the peak value of the output to the peak value of the
input:
= = [2-22]
This equation clearly shows that gain is inversely proportional to frequency.
11
Lecture 02 Applications of Operational Amplifiers

Although high-quality, precision integrators are constructed as shown in Fig. 2-16

for use in low-frequency applications such as analog computers, these applications require
high-quality amplifiers with extremely small offset voltages. As mentioned earlier, any
input offset is integrated as if it were a dc signal input and will eventually cause the
amplifier to saturate. To eliminate this problem in practical integrators using general
purpose amplifiers, a resistor is connected in parallel with the feedback capacitor, as
shown in Fig. 2-17. Since the capacitor is an open circuit as dc is concerned, the dc closed-
loop gain of the integrator is –Rf/R1. At high frequencies, XC is much smaller than Rf, so
the parallel combination of C and Rf is essentially the same as C alone, and signals are
integrated as usual.

Fig. 2-17

While the feedback resistor in Fig. 2-17 prevents integration of dc inputs, it also
degrades the integration of low-frequency signals. At frequencies where the capacitive
reactance of C is comparable in value to Rf, the net feedback impedance is not
predominantly capacitive and true integration does not occur. As a rule, we can say that
satisfactory integration will occur at frequencies much greater than the frequency at which
XC = Rf. That is, for integrator action we want
<< => << =>
>> [2-23]
The frequency fc where XC = Rf,
= [2-24]
Eqn. [2-24] defines a break frequency, fc, in the Bode plot of the practical integrator.
As shown in Fig. 2-18, at frequencies well above fc, the gain falls off at the rate of
−20 dB/decade, like that of an ideal integrator, and at frequencies below fc, the gain
approaches its dc value of Rf/R1. Because the integrator's output amplitude or gain
decreases with frequency, it is a kind of low-pass filter.

12
Lecture 02 Applications of Operational Amplifiers

Fig. 2-18

In closing our discussion of integrators, we should note that it is possible to scale

and integrate several input signals simultaneously, using an arrangement similar to the
linear combination circuit studied earlier. Fig. 2-19 shows a practical, three-input
integrator that performs the following operation at frequencies above fc:
= −∫ + +
=− ∫ − ∫ − ∫ [2-25]
If R1 = R2 = R3 = R, then
= ∫( + + ) [2-26]

Fig. 2-19

13
Lecture 02 Applications of Operational Amplifiers

Exercise 2-9:
(a) Find the peak value of the output of the ideal integrator shown in Fig. 2-20. The
input is vin = 0.5 sin (100t) V.
(b) Repeat, when vin = 0.5 sin (10 3t) V.
[Answers: (a) vo = 5 cos (100t) V => peak value = 5 V,
(b) vo = 0.5 cos (1000t) V => peak value = 0.5 V]

Fig. 2-20

Exercise 2-10:
Design a practical integrator that
(a) integrates signals with frequencies down to 100 Hz, and
(b) produces a peak output of 0.1 V when vin is a 10 V peak sine wave at frequency
10 kHz. Choose C = 0.01 µF.
Find the dc component in the output when there is a +50 mV dc input.
[Answer: Rf = 1.59 MΩ, R1 = 159 kΩ, Rc = 145 kΩ, vo = − 0.5 V, Fig. 2-21]

Fig. 2-21

14
Lecture 02 Applications of Operational Amplifiers

2.5 Op-Amp differentiators:

An electronic differentiator produces an output waveform whose value at any instant of
time is equal to the rate of change of the input at that point in time. Fig. 2-22 demonstrates
the operation of an ideal electronic differentiator. The input is the ramp voltage vin = Et.
The rate of change, or slope, of this ramp is a constant E volts/second. Since the rate of
change of the input is constant, we see that the output of the differentiator is the constant
dc level E volts. We would write
( )
= = [2-27]

Fig. 2-22

Fig. 2-23 shows how an ideal differentiator is constructed using an operational

amplifier. Note that we now have a capacitive input and a resistive feedback-again, just the
opposite of an integrator. It can be shown that the output of this differentiator is
=− [2-28]
Now, we can show how the circuit of Fig. 2-23 performs differentiation. Since the
current into the − terminal is 0, we have, from Kirchhoff's current law, + = 0.
Since = 0, = and = .
Also, = , so + = 0 or =− .
If the input to the inverting integrator in Fig. 2- 23 is vin = A sin ωt, the output is
( )
=− =− cos( ) = sin( − 90° ) [2-29]
Eqn. [2-29] shows that when the input is sinusoidal, the amplitude of the output of a
differentiator is directly proportional to frequency. Also the output lags the input by 90 °,
regardless of frequency. The gain of the differentiator is
= = [2-30]

Fig. 2-23
15
Lecture 02 Applications of Operational Amplifiers

In a practical differentiator, the amplification of signals in direct proportion to their

frequencies cannot continue indefinitely as frequency increases, because the amplifier has
a finite bandwidth. As we have already known, there is some frequency at which the
output amplitude must begin to fall off. Nevertheless, it is often desirable to design a
practical differentiator so that it will have a break frequency even lower than that
determined by the upper cutoff frequency of the amplifier, that is, to roll off its gain
characteristic at some relatively low frequency. This action is accomplished in a practical
differentiator by connecting a resistor in series with the input capacitor, as shown in
Fig. 2-24. We can understand how this modification achieves the stated goal by
considering the net impedance of the R1C combination at low and high frequencies:
= − ⁄ =>
| |= + (1⁄ ) .
At very small values of ω, Zin, is dominated by the capacitive reactance component, so the
combination is essentially the same as C alone, and differentiator action occurs. At very
high values of ω, 1/ωC is negligible, so Zin is essentially the resistance R1, and the circuit
behaves like an ordinary inverting amplifier.

Fig. 2-24

The break frequency fb beyond which differentiation no longer occurs in Fig. 2-24 is
the frequency at which XC = R1:
= = => = [2-31]
In designing a practical differentiator, the break frequency should be set well above the
highest frequency at which accurate differentiation is desired:
>> [2-32]
where fh is the highest differentiation frequency. Fig. 2-25 shows Bode plots for the gain
of the ideal and practical differentiators. In the low-frequency region where differentiation
occurs, note that the gain rises with frequency at the rate of 20 dB/decade. The plot shows
that the gain levels off beyond the break frequency fb and then falls off at −20 dB/decade
beyond the amplifier's upper cutoff frequency. Recall that the closed-loop bandwidth, or
upper cutoff frequency of the amplifier, is given by
= [2-33]
where β in this case is R1/(R1 + Rf).

16
Lecture 02 Applications of Operational Amplifiers

Fig. 2-25

Exercise 2-11:
(a) Design a practical differentiator that will differentiate signals with frequencies up to
200 Hz. The gain at 10 Hz should be 0.1. Choose fb = 10 fh, and C = 0.1 µF.
(b) If the operational amplifier used in the design has a unity-gain frequency of 1 MHz,
what is the upper cutoff frequency of the differentiator?
[Answer: (a) R1 = 796 Ω, Rf = 15.9 kΩ, Fig. 2-26(a)
(b) f2 = 47.7 kHz, Fig. 2-26(b)]

(a)

(b)
Fig. 2-26
17
Lecture 02 Applications of Operational Amplifiers

2.6 Instrumentation Amplifiers:

An amplifier can be operated in a differential mode to produce an output voltage
proportional to the difference between two input signals. Differential operation is a
common requirement in instrumentation systems and other signal-processing applications
where high accuracy is important. Fig 2-27 shows an improved configuration for
producing an output proportional to the difference between two inputs. Notice that the
circuit is basically the difference amplifier discussed earlier, with the addition of two input
stages. Each input signal is connected directly to the noninverting terminal of an
operational amplifier, so each signal source sees a very large input resistance. This circuit
arrangement is so commonly used that it is called an instrumentation amplifier and is
commercially available by that name in single-package units. These devices use closely
matched, high-quality amplifiers and have very large common-mode rejection ratios.

Fig. 2-27

In our analysis of the instrumentation amplifier, we will refer to Fig. 2.28, which
shows current and voltage relations in the circuit. we begin by noting that the usual
assumption of ideal amplifiers allows us to equate vi+ and vi− at each input amplifier
(vi+ − vi− ≈ 0), with the result that input voltages v1 and v2 appear across adjustable resistor
RA in Fig. 2-28. For analysis purposes, let us assume that v1 > v2. Then, the current i
through RA is
= .
Since no current flows into either amplifier input terminal, the current i must also flow in
each resistor R connected on opposite sides of RA. Therefore, the voltage drop across each
of those resistors is
( )
= = [2-34]
18
Lecture 02 Applications of Operational Amplifiers

The output voltages vo1 and vo2 are given by

= +
= − [2-35]
Voltages vo1 and vo2 are the input voltages to the differential stage. Since the external
resistors connected to that stage are all equal to R, we recall (with A = 1) that
= −
= ( + )−( − ) = − +2
( )
= − + =>
=( − ) 1+ [2-36]
Eqn. 2-36 shows that the output of the instrumentation amplifier is directly proportional to
the difference voltage (v1 and v2), as required. The overall closed-loop gain is
= 1+ [2-37]
RA is made adjustable so that gain can be easily adjusted for calibration purposes. Note that
the gain is inversely proportional to RA.
To ensure proper operation of the instrumentation amplifier, all three of the
following inequalities must be satisfied at all times:
1+ − < ( ) [2-38]
1+ − < ( ) [2-39]
1+ | − |< ( ) [2-40]
where Vmax(1) is the maximum output voltage of each input stage and Vmax(2) is the
maximum output voltage of the differential (output) stage.

Fig. 2-28

19
Lecture 02 Applications of Operational Amplifiers

Exercise 2-12:
(a) Assuming ideal amplifiers, find the minimum and maximum output voltage Vo, that
is, Vo(min) and Vo(max), of the instrumentation amplifier shown in Fig. 2-29 when
the l0 kΩ potentiometer Rp is adjusted through its entire range.
(b) Find Vo1 and Vo2 when Rp is set in the middle of its resistance range.
[Answers: (a) Vo(min) = 1.45 V, Vo(max) = 20.5 V,
(b) Vo1 = 1.209 V, Vo2 = −1.109 V]

Fig. 2-29

Exercise 2-13:
The maximum output voltages for all three operational amplifiers in an instrumentation
amplifier are +15 V. For a particular application, it is known that input signal v1 may vary
from 0 V to 0.8 V and input signal v2 from 0 V to 1.3 V. Assuming that R = 2 kΩ, design
the circuit for maximum possible closed-loop gain.
[Answer: RA > 112.68 Ω, RA > 173.30 Ω, RA > 189.71 Ω,
RA > 106.67 Ω, RA > 379.56 Ω, RA > 225.35 Ω,
RA(max) ≈ 390 Ω (standard/largest resistor),
vo/(v1 − v2) = 11.26]

20
 Subject: PHYSICS
TOPIC:
Cathode Ray
Oscilloscope (CRO)
SEM-IV(GE)
 Definition:
The cathode ray oscilloscope (CRO) is a type of electrical
instrument which is used for showing the measurement
and analysis of waveforms and others electronic and
electrical phenomenon. It is a very fast X-Y plotter shows
the input signal versus another signal or versus time.
The CROs are used to analyse the waveforms, transient,
phenomena, and other time-varying quantities from a
very low-frequency range to the radio frequencies.
CRT =Cathode Ray Tube
CRT =Cathode Ray Tube
 a) Voltage Measurement
The most direct voltage measurement made with an oscilloscope is the peak-peak
value. The rms value of the voltage can easily be calculated from the peak to peak
measurement if desired. The peak to peak value of voltage is compute as
Vp-p = (vertical p-p division) x volts/div

Figure: The peak-peak

voltage of a waveform
is measured by
multiplying the
VOLTS/DIV setting by
the peak-peak vertical
divisions occupied by
the waveform. The
time period is
determined by
multiplying the
horizontal divisions
for one cycle by the
TIME/DIV setting.
 Refer to figure 3, find the peak-peak voltages for each wave.
Wave A : Vp-p =(4.6 divisions) x 100 mV = 460 mV
Wave B : Vp-p = (2 divisions) x 100mV = 200mV

(b) Period and frequency measurement

The time period of a sine wave is determined by measuring the
time for one cycle in horizontal divisions and multiplying by setting
of the time/div control
Period, T = (horizontal divisions / cycle) (time / div)
Frequency, f = 1 / T
 (c) Phase difference measurement
Phase difference, θ = (phase difference in
divisions) x (degree/div)
Example
The phase difference between two waveforms is measured by the method
illustrated in figure .

Each wave has a time period of 8

horizontal divisions, and the time
between commencements of each cycle
is 1.4 div
one cycle = 8 div = 360 degree
1 div= 45 degree
Thus, the phase different is
θ = (1.4)(45degree/div)
= 63degree
 PHOTO-DIODE

The photodiode is a semiconductor p-n junction device whose region of

operation is limited to the reverse biased region. The Fig shows the symbol of
photodiode while the Fig shows the working principle of photodiode.

The photodiode is connected in reverse biased condition. The depletion region width is
large. Under normal condition, it carries small reverse current due to
minority charge carriers. When light is incident through glass window on the p-n
junction, photons in the light bombard the p-n junction and some energy is imparted
to the valence electrons. Due to this, valence electrons are dislodged from the
covalent bonds and become free electrons. Thus more electron-hole pairs are
generated. Thus total number of minority charge carriers increases and hence the reverse
current increases. This is the basic principle of operation of photodiode.

The reverse current without light in diode is in the range of micro amperes. The
change in this current due to the light is also in the range of micro amperes. Thus such a
change can be significance observed in the reverse current. If the photodiode
is forward biased, the current flow through it is in mA. The applied forward biased
voltage takes the control of the current instead of the light. The change in forward
current due to light is negligible and can not be noticed. The resistance of forward
biased diode is not affected by the light. Hence to have significant effect of light on
the current and to operate photodiode as a variable resistance device, it is always
connected in reverse biased condition.

The Fig shows the small signal model for photodiode. Photodiode is represented by an ideal
junction diode in parallel with a current source which is proportional to the light intensity.

Advantages

The advantages of photodiode are,

1.Can be used as variable resistance device.

2.Highly sensitive to the light.

3.The speed of operation is very high. The switching of current and hence the resistance value
from high to low or otherwise is very fast.

Disadvantages

The various disadvantages of photodiode are,

1.The dark current is temperature dependent.

 2.The overall photodiode characteristics are temperature dependent hence have poor

3.temperature stability.

4.The current and change in current is in the range of 1 which may not be
sufficient to drive other circuits. Hence amplification is necessary.

Photodiode Applications

The two commonly used systems using photodiode are alarm system and a counting system.

Source : http://mediatoget.blogspot.in/2011/09/photo-diode.html
10.7: Diodes, LEDs and Solar Cells
Diodes are semiconductor devices that allow current to flow in only one direction. Diodes act as rectifiers in electronic
circuits, and also as efficient light emitters (in LEDs) and solar cells (in photovoltaics). The basic structure of a diode is a
junction between a p-type and an n-type semiconductor, called a p-n junction. Typically, diodes are made from a single
semiconductor crystal into which p- and n- dopants are introduced.

Closeup of a diode, showing the square-shaped semiconductor crystal (black object on left).

If the n-side of a diode is biased at positive potential and the p-side is biased negative, electrons are drawn to the n-side
and holes to the p-side. This reinforces the built in potential of the p-n junction, the width of the depletion layer increases,
and very little current flows. This polarization direction is referred to as "back bias." If the diode is biased the other way,
carriers are driven into the junction where they recombine. The electric field is diminished, the bands are flattened, and
current flows easily since the applied bias lowers the built-in potential. This is called "forward bias."

Electrons (red) and holes (white) in a forward-biased diode.

The figure on the left illustrates a forward-biased diode, through which current flows easily. As electrons and holes are
driven into the junction (black arrows in lower left figure), they recombine (downward blue arrows), producing light
and/or heat. The Fermi level in the diode is indicated as the dotted line. There is a drop in the Fermi level (equal to the
applied bias) across the depletion layer. The corresponding diode i-V curve is shown on the right. The current rises
exponentially with applied voltage in the forward bias direction, and there is very little leakage current under reverse bias.
At very high reverse bias (typically tens of volts) diodes undergo avalanche breakdown and a large reverse current flows.

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Diode i-V curve

A light-emitting diode or LED is a kind of diode that converts some of the energy of electron-hole recombination into
light. This radiative recombination process always occurs in competition with non-radiative recombination, in which the
energy is simply converted to heat. When light is emitted from an LED, the photon energy is equal to the bandgap energy.
Because of this, LED lights have pure colors and narrow emission spectra relative to other light sources, such as
incandescent and fluorescent lights. LED lights are energy-efficient and thus are typically cool to the touch.

Light-emitting diode (LED).

Direct-gap semiconductors such as GaAs and GaP have efficient luminescence and are also good light absorbers. In
direct gap semiconductors, there is no momentum change involved in electron-hole creation or recombination. That is, the
electrons and holes originate at the same value of the momentum wavevector k, which we encountered in Ch. 6. k is
related to the momentum (also a vector quantity) by p = hk/2π. In a direct-gap semiconductor, the top of the valence band
and the bottom of the conduction band most typically both occur at k = 0. Since the momentum of the photon is close to
zero, photon absorption and emission are strongly allowed (and thus kinetically fast). Polar semiconductors such as GaAs,
GaN, and CdSe are typically direct-gap materials. Indirect-gap semiconductors such as Si and Ge absorb and emit light
very weakly because the valence band maximum and conduction band minimum do not occur at the same point in k-
space. This means that a lattice vibration (a phonon) must also be created or annihilated in order to conserve momentum.
Since this "three body" (electron, hole, phonon) process has low probability, the radiative recombination of electrons and
holes is slow relative to non-radiative decay - the thermalization of electron-hole energy as lattice vibrations - in indirect-
gap semiconductors. The momentum selection rule thus prevents light absorption/emission and there are no pure Si LEDs
or Si-based lasers.

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Prof. Shuji Nakamura holding a blue LED.

While red, orange, yellow, and green LEDs can be fabricated relatively easily from AlP-GaAs solid solutions, it was
initially very difficult to fabricate blue LEDs because the best direct gap semiconductor with a bandgap in the right energy
range is a nitride, GaN, which is difficult to make and to dope p-type. Working at Nichia Corporation in Japan, Shuji
Nakamura succeeded in developing a manufacturable process for p-GaN, which is the basis of the blue LED. Because of
the importance of this work in the development of information storage (Blu-Ray technology) and full-spectrum, energy-
efficient LED lighting, Nakamura shared the 2014 Nobel Prize in Physics with Isamu Asaki and Hiroshi Amano, both of
whom had made earlier contributions to the development of GaN diodes.
A Solar cell, or photovoltaic cell, converts light absorbed in a p-n junction directly to electricity by the photovoltaic
effect. Photovoltaics is the field of technology and research related to the development of solar cells for conversion of
solar energy to electricity. Sometimes the term solar cell is reserved for devices intended specifically to capture energy
from sunlight, whereas the term photovoltaic cell is used when the light source is unspecified.

Photovoltaic effect in a semiconductor p-n junction

Photocurrent in p-n junction solar cells flows in the diode reverse bias direction. In the dark, the solar cell simply acts as a
diode. In the light, the photocurrent can be thought of as a constant current source, which is added to the i-V characteristic
of the diode. The relationship between the dark and light current in a photovoltaic cell is shown in the diagram at the left.

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Current-voltage characteristic of a solar cell in the dark and under illumination with band gap light. The short-circuit photocurrent is
indicated as isc, and the open-circuit photovoltage is Vphoto. The maximum power generated by the solar cell is determined by the area of the
orange box.

The built-in electric field of the p-n junction separates e- h+ pairs that are formed by absorption of bandgap light in the
depletion region. The electrons flow downhill, towards the n-type side of the junction, the holes flow uphill towards the p-
side. If hν ≥ Egap, light can be absorbed by promoting an electron from the valence band to the conduction band. Any
excess energy is rapidly thermalized. Light with hν > Eg thus can store only Eg worth of energy in an e- h+ pair. If light is
absorbed outside of depletion region, i.e., on the n- or p-side of the junction where there is no electric field, minority
carriers must diffuse into the junction in order to be collected. This process occurs in competition with electron-hole
recombination. Because impurity atoms and lattice defects make efficient recombination centers, semiconductors used in
solar cells (especially indirect-gap materials such as Si, which must be relatively thick in order to absorb most of the solar
spectrum) must be very pure. Most of the cost of silicon solar cells is associated with the process of purifying elemental
silicon and growing large single crystals from the melt.
In the photodiode i-V curve above, Vphoto is typically only about 70% of the bandgap energy Egap. The photocurrent is
limited by the photon flux, the recombination rate, and the re-emission of absorbed light.[6] The area of the orange
rectangle indicates the power generated by the solar cell, which can be calculated as P = i x V. In good single crystal or
polycrystalline solar cells made of Si, GaAs, CdTe, CuInxGa1-xSe2, or (CH3NH3)PbI3 the quantum yield (the ratio of short
circuit photocurrent to photon flux) is close to unity.

The equivalent circuit of a p-n junction solar cell, which results in the "light" i-V curve shown in the figure above. The solar cell is
effectively a diode with a reverse-bias current source provided by light-generated electrons and holes. The shunt resistance (Rsh) in the
equivalent circuit represents parasitic electron-hole recombination. A high shunt resistance (low recombination rate) and low series
resistance (Rs) are needed for high solar cell efficiency.

Solar cells have many current applications. Individual cells are used for powering small devices such as electronic
calculators. Photovoltaic arrays generate a form of renewable electricity, particularly useful in situations where electrical
power from the grid is unavailable such as in remote area power systems, Earth-orbiting satellites and space probes,
remote radio-telephones and water pumping applications. Photovoltaic electricity is also increasingly deployed in grid-
tied electrical systems.
The cost of installed photovoltaics (calculated on a per-watt basis) has dropped over the past decade at a rate of about 13%
per year, and has already reached grid parity in Germany and a number of other countries.[7] Photovoltaic grid parity is
anticipated in U.S. power markets in the 2020 timeframe.[8] A major driver in the progressively lower cost of photovoltaic

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power is the steadily increasing efficiency of solar cells, which is shown in the graphic at the right. Higher efficiency solar
cells require less area to deliver the same amount of power, and this lowers the "balance of system" costs such as wiring,
roof mounting, etc., which scale as the area of the solar panels. Progress towards higher efficiency reflects improved
processes for making photovoltaic materials such as silicon and gallium arsenide, as well as the discovery of new
materials. Silicon solar cells are a mature technology, so they are now in the flat part of the learning curve and are
approaching their maximum theoretical efficiencies. Newer technologies such as organic photovoltaics, quantum dot solar
cells, and lead halide perovskite cells are still in the rising part of the learning curve.

Reported timeline of solar cell energy conversion efficiencies since 1976 (National Renewable Energy Laboratory)

A field effect transistor (FET) is a transistor that uses an electric field to control the width of a conducting channel and
thus the current in a semiconductor material. It is classified as unipolar transistor, in contrast to bipolar transistors.
Field effect transistors function as current amplifiers. The typical structure of Si-based FETs is one in which two n-type
regions (the source and the drain) are separated by a p-type region. An oxide insulator over the p-type region separates a
metal gate lead from the semiconductor. This structure is called a metal-oxide-semiconductor FET (or MOSFET). When
voltage is applied between source and drain, current cannot flow because either the n-p or the p-n junction is back-biased.
When a positive potential is applied to the gate, however, electrons are driven towards the gate, and locally the
semiconductor is "inverted" to n-type. Then the current flows easily between the n-type source and drain through the n-
channel. The current flow between the source and drain is many times larger than the current through the gate, and thus
the FET can act as an amplifier. Current flow can also represent a logical "1," so FETs are also used in digital logic.

Cross section of an n-type MOSFET

In electronic devices such as microprocessors, field-effect transistors are kept in the off-state most of the time in order to
minimize background current and power consumption. The FET shown above, which has n-type source and drain regions,
is called an NMOS transistor. In a PMOS transistor, the source and drain regions are p-type and the gate is n-type. In
CMOS (complementary metal-oxide semiconductor) integrated circuits, both NMOS and PMOS transistors are used.
CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the voltage source

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or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another
NMOS transistor. This arrangement results in low static power consumption.

Transistors are most useful in the range of gate voltage (indicated by the red circle in the figure at the left) where the
source-drain current changes rapidly. In this region it is possible to effect a large change in current between source and
drain when a small signal is applied to the gate. An important figure of merit for FETs is the subthreshold slope, which is
the slope a plot of log(current) vs. Vgate. An ideal subthreshold slope is one decade of current per 60 mV of gate bias.
Typically, a decade change in source-drain current can be achieved with a change in gate voltage of ~70 mV. The
performance of FETs as switches and amplifiers is limited by the subthreshold slope, which in turn is limited by the
capacitance of the gate. It is desirable to have a very high gate capacitance, which requires a thin insulating oxide, but also
to have a small leakage current, which requires a thick oxide. A current challenge in the semiconductor industry is to
continue to scale FETs to even smaller nanoscale dimensions while maintaining acceptable values of these parameters.
This is being done by developing new gate insulator materials that have higher dielectric constants than silicon oxide and
do not undergo redox reactions with silicon or with metal gate leads. Only a few known materials (such as hafnium
oxynitride and hafnium silicates) currently meet these stringent requirements.

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