CS 221

LOGIC DESIGN
Fall 2014

1 By Wessam El-Behaidy
Assistant Professor ,
Computer Science Department
REMEMBER OUR RULES

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 SYNCHRONOUS SEQUENTIAL
LOGIC
3 Lecture 9
SEQUENTIAL CIRCUIT

Feedback path
 The state of sequential circuit defined by:
 The binary information stored in memory elements
at any given time
 The outputs in a sequential circuit is a function
of:
 Inputs

Section 5.2
 Present state 4
MAIN TYPES OF SEQUENTIAL CIRCUITS
 Synchronous sequential circuit
 Asynchronous sequential circuit

Section 5.2
5
SYNCHRONOUS SEQUENTIAL CIRCUITS
 Synchronous circuit that use clock pulses to control
storage elements

 Master clock generator

 It supplies a continuous train of clock pulses
 The pulses are applied to all flip-flops and registers in
the system

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CLOCKED SEQUENTIAL CIRCUITS
 Synchronous circuit that use clock pulses to
control storage elements is called clocked
sequential circuits
 Also called Synchronous circuit, because
updating in storage element is synchronized to
the occurrence of clock pulses

Section 5.2
7
SYNCHRONOUS CLOCKED SEQUENTIAL
CIRCUIT

Clock

Section 5.2
(clk)
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STORAGE ELEMENTS
 Various types:
 Latches: operate with signal level
 Flip-flops: controlled by a clock transition

 They differ in :
 the number of inputs they possess and
 The manner in which the inputs affect the binary
state
 Latches are the basic circuits from which the flip-
flops are constructed

Section 5.3
9
 Q=1  set state Q=0 Reset state

GRAPHIC SYMBOLS FOR LATCHES

Q Q Q

Q’ Q’ Q’

Section 5.3
10
 NAND: (x.0)’=1
(x.1)’=x’

D LATCH (TRANSPARENT LATCH)

 To eliminate the undesirable condition in SR
latch
1 1
0 0
01 0
1 1
S’R’ latch
1 0 Cross-coupled
1 NAND gate
0
1 0 1
1 1
0 0

Control input

Section 5.3
11
TRIGGER
 The state of a latch or flip-flop is switched by a
change in the control input, this momentary
change is called a trigger.

Section 5.4
12
D LATCH TRIGGER
 The D latch with pulses in the control input is
triggered every time the pulse goes to the logic 1.

As long as the pulse input remains at this level,

any changes in the data input will change the
output and the state of the latch.

Section 5.4
13
LATCH PROBLEM

 When latches are used for storage element,

 If the inputs applied to the latches change while the
clock pulse is still at logic-1 level
 The latches will respond to the new values and a new
output state may occur

Section 5.4
 The result is an unpredictable situation, 14

 the flip-flops are used

FLIP-FLOP TRIGGER
 The problem with the latch is that respond to a
change in the level of a clock pulse
 The key to the proper operation of a flip-flop is to
trigger it only during a signal transition

Section 5.4
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FLIP-FLOPS

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A FLIP-FLOP FROM A LATCH

 There are 2 ways:

1.Master/slave edge triggered D flip-flop
Employ 2 latches in a special configuration that:
1. isolates the output of the flip-flop
2. Prevents it to be affected while the input is
changing
2. It uses 3 latches:
2 latches respond to the external D (data) and Clk
(clock) and the 3rd provides the outputs for the flip-flop
1. triggers only during signal transition of
synchronizing signal (clock)

Section 5.4
2. Is disabled during the rest of the clock pulse 17
MASTER-SLAVE EDGE –TRIGGERED D
FLIP-FLOP
 Constructed with 2 D latches and an inverter
First latch: called master, Second latch: called slave

Section 5.4
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BEHAVIOR OF MASTER-SLAVE FLIP-FLOP
 Its behavior dictates that:
 The output may change once
 A change in the output is triggered by the negative
edge of the clock
 The change may occur only during the clock’s
negative level
 Note :
The value that is produced at the output is that
value that as stored in the master stage
immediately before the negative edge occurred
 Can we design the circuit to be triggered by

Section 5.4
positive edge? 19
GRAPHICAL SYMBOL FOR EDGE-TRIGGERED
D FLIP-FLOP

D Flop-flop characteristic table

Next state

Section 5.4
20
JK FLIP-FLOP Next state
K Present state
 D=JQ’ + K’Q
Q
J 1 Q’

Section 5.4
21

Why D flip-flop ?
T FLIP-FLOP

 T for (toggle) is a complementing flip-flop

D= T + Q = TQ’ +T’Q
 Used for designing binary counters

Section 5.4
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CHARACTERISTIC EQUATIONS
The logical properties of a flip-flop, described in the
characteristic table, can be expressed algebraically
 D flip-flop

Q(t+1)= D
 JK flip-flop

Q(t+1)= JQ’ +K’Q

 T flip-flop

Q(t+1)= T + Q = TQ’ +T’Q

Section 5.4
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ASYNCHRONOUS SEQUENTIAL CIRCUIT:
DIRECT INPUTS
 Some flip-flops have asynchronous inputs that are
used to force the flip-flop to a particular state
independently of the clock
 The input that set the flip flop to 1 is called preset or
direct set
 The input that set the flip flop to 0 is called clear or
direct reset
 When power is turned on in a digital system, the
state of the flip-flop is unknown
 The direct inputs are useful for bringing all flip-flops to
a known state prior the clocked operation

Section 5.4
24
D-FLIP-FLOP WITH ASYNCHRONOUS RESET

0
1
1

Error in book

Section 5.4
25
ANALYSIS OF CLOCKED SEQUENTIAL
CIRCUITS

 Analysis of clocked sequential circuits

 describes what a given circuit will do under
certain operating conditions
 Behavior of clocked sequential circuit
 is determined from the inputs, the outputs, and
the state of its flip-flops (present state)
 The analysis of a sequential circuits consists of
obtaining:
 State table (transition table) or
 State diagram
 It is also possible to write Boolean expressions that

Section 5.5
describe the behavior of the sequential circuit  26
state equations (state equation)
STATE EQUATIONS
 The sequential
circuit consists of:
 Two D flip-flops (A and B)
 An input x
 An output y
 Determine next state
of D flip-flops:
 A(t+1)= A(t)x(t) +B(t) x(t)
 B(t+1) = A’(t) x(t)
 The present state of
the output y: State equation

Section 5.5
specifies the next state as
 y(t)= [A(t)+B(t)]x’(t) a function of the present state
27

and inputs
 STATE TABLE
1. The state equations:
 A(t+1)= Ax +B x
 B(t+1) = A’ x
2 flip-flops:
2.  y= (A+B)x’ A and B

1 Based on

Section 5.5
state equations 28
1

1
TWO FORMS OF STATE TABLE

Section 5.5
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STATE DIAGRAM
 The information available in a state table can be
represented graphically in the form of a state
diagram Input/output
Present state

Section 5.5
We have 2 flip-flops 30
 we have 22 states (= 4 )
 we have 4 circles (=present states)
FLIP-FLOP INPUT EQUATIONS
 Output equations:
 A set of Boolean functions describes the part of the
combinational circuit that generates external outputs
 Flip-flop Input equations (excitation equations):
 A set of Boolean functions describes the part of the circuit
that generates the inputs to the flip-flops
 Ex: DQ= x+y
 The following input equation specifies an OR gate with
inputs x and y connected to D input of a flip-flop whose
output is labeled with the symbol Q
 Previous example (fig. 5.15)
 DA= Ax +Bx

Section 5.5
 DB = A’ x
 y= (A+B)x’
ANALYSIS WITH D FLIP-FLOPS
 DA= A + x + y

Section 5
32

For D flip-flop, state equation is the same as the input equation

MEALY AND MOORE MODELS
Two models of sequential circuits:
1. Mealy model (Mealy FMS or Mealy machine )

the output is a function of both the present state

and the input
2. Moore model (Moore FMS or Moore machine )

the output is a function of only the present state

A circuit may have both types of outputs

Section 5.5
33
MEALY MODELS EXAMPLE

Input/output
Present state

Section 5.5
34
MOORE MODELS EXAMPLE1

Section 5.5
35
MOORE MODELS EXAMPLE2

Section 5.5
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 THANKS
We covered from:
Ch.5 (5.2-5.4)
Assignment Ch5: 1, 2, 3, 4, 5, 6, 7
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