COMPSCI 205

Computer Organization
and Programming

Chapter 2
Instructions: Language of
the Computer
Instructor: Ming-Chun Huang, Ph.D.
[email protected]

EECS314 Introduction.1 Spring, 2014

Processor Organization

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 Components of a Computer

q Same components for

The BIG Picture
all kinds of computer
● Desktop,
server,
embedded

q Input/output includes
● User-interface devices
- Display, keyboard, mouse
● Storage devices
- Hard disk, CD/DVD, flash
● Network adapters
- For communicating with other
computers

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 Example Machine Organization
q All computers in the world would consist of the following
major components
q For a Workstation, typically a system designer allocates
● 25% of cost on processor
● 25% of cost on memory (minimum memory size)
● Rest on I/O devices, power supplies, box

Computer
CPU Memory Devices

Control Input

Datapath Output

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 Processor Organization

A very simple
processor
and memory

Inside a
simple
processor

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 Inside the Processor (CPU)
q Datapath: performs operations on data
q Control: sequences datapath, memory, ...
q Cache memory
● Small fast SRAM memory for immediate access to data

q Apple A5

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 (von Neumann) Processor Organization
q Control needs to CPU Memory Devices
1. input instructions from Memory
Control Input
2. issue signals to control the
information flow between the Datapath Output
Datapath components and to
control what operations they
perform Fetch
3. control instruction sequencing

q Datapath needs to have the Exec Decode

● components – the functional units and

storage (e.g., register file) needed to execute instructions
● interconnects - components connected so that the instructions can
be accomplished and so that data can be loaded from and stored
to Memory

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 ISA vs. Microarchitecture

q An ISA or Instruction Set Architecture describes

the aspects of a computer architecture visible to the
low-level programmer, including the native datatypes,
instructions, registers, addressing modes, memory
architecture, interrupt and exception handling, and I/
O organization.

q Microarchitecture is the set of

internal processor design techniques
used to implement the instruction set
(including microcode, pipelining,
cache systems etc.)

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 The Big Picture: CISC vs. RISC
CISC RISC
(Complex Instruction Set Reduced Instruction Set
Computer) Computer)
1. Includes multi-clock 1. Single-clock,
complex instructions reduced instruction only
2. Memory-to-memory: 2. Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in are independent
instructions instructions
3. Small code sizes, 3. Large code sizes, Low
high cycles per second cycles per second

4. Spends more
4. Transistors used for transistors
storing/executing on memory registers
CISC RISC complex instructions
ADD 2:3, 5:2 LOAD A, 2:3 5. Emphasis on 5. Emphasis of software
LOAD B, 5:2 hardware
ADD A, B 6. Intel Pentium 6. ARM, DEC Alpha, PA-
STORE 2:3, A RISC, SPARC, MIPS, and
IBM PowerPC.
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 RISC - Reduced Instruction Set Computer
q RISC philosophy
● Fixed instruction lengths
● Load-store instruction sets
● Limited addressing modes
● Limited operations

q Instruction sets are measured by how well

compilers use them as opposed to how well
assembly language programmers use them

Design goals: speed, cost (design, fabrication, test,

packaging), size, power consumption, reliability,
memory space (embedded systems)
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 The MIPS Instruction Set
q Used as the example throughout the book
q Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
q Large share of embedded core market
● Applications in consumer electronics, network/storage
equipment, cameras, printers, …

q Typical of many modern ISAs

● See MIPS Reference Data tear-out card, and
Appendixes B and E

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 §2.5 Representing Instructions in the Computer
Representing Instructions
q Instructions are encoded in binary
● Called machine code

q MIPS instructions
● Encoded as 32-bit instruction words
● Small number of formats encoding operation code
(opcode), register numbers, …
● Regularity!

q Register numbers
● $t0 – $t7 are reg s 8 – 15
● $t8 – $t9 are reg s 24 – 25

● $s0 – $s7 are reg s 16 – 23

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 Register Usage
q $a0 – $a3: arguments (reg s 4 – 7)
q $v0, $v1: result values (reg s 2 and 3)
q $t0 – $t9: temporaries (Can be overwritten by callee)
q $s0 – $s7: saved (Must be saved/restored by callee)
q $gp: global pointer for static data (reg 28)
q $sp: stack pointer (reg 29)
q $fp: frame pointer (reg 30)
q $ra: return address (reg 31)

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 §2.2 Operations of the Computer Hardware
Arithmetic Operations
q Add and subtract, three operands
● Two sources and one destination

add a, b, c # a gets b + c
q All arithmetic operations have this form
q Design Principle 1: Simplicity favours regularity
● Regularity makes implementation simpler
● Simplicity enables higher performance at lower cost

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 MIPS R-format Instructions

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

q Instruction fields
● op: operation code (opcode)
● rs: first source register number
● rt: second source register number
● rd: destination register number
● shamt: shift amount (00000 for now)
● funct: function code (extends opcode)

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 R-format Example

op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

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 10002
…>>2…
00102
fill with zeros

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 -8=10002
…>>2…
-2=11102
fill with ones

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 MIPS I-format Instructions

op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

q Immediate arithmetic and load/store instructions

● rt: destination or source register number
● Constant: –215 to +215 – 1
● Address: offset added to base address in rs

q Design Principle 4: Good design demands good

compromises
● Different formats complicate decoding, but allow 32-bit
instructions uniformly
● Keep formats as similar as possible
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 Immediate Operands
q Constant data specified in an instruction

addi $s3, $s3, 4

q No subtract immediate instruction
● Just use a negative constant
addi $s2, $s1, -1
q Design Principle 3: Make the common case fast
● Small constants are common
● Immediate operand avoids a load instruction

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 §2.7 Instructions for Making Decisions
Conditional Operations
q Branch to a labeled instruction if a condition is true
● Otherwise, continue sequentially

q beq rs, rt, L1

● if (rs == rt) branch to instruction labeled L1;

q bne rs, rt, L1

● if (rs != rt) branch to instruction labeled L1;

q j L1
● unconditional jump to instruction labeled L1

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 Compiling If Statements
q C code:
if (i==j) f = g+h;
else f = g-h;
● f, g, … in $s0, $s1, …

q Compiled MIPS code:

bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: …
Assembler calculates addresses

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 Compiling Loop Statements
q C code:
while (save[i] == k) i += 1;
● i in $s3, k in $s5, address of save in $s6

q Compiled MIPS code:

Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit: …

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 Multiplied by 4

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 More Conditional Operations
q Set result to 1 if a condition is true
● Otherwise, set to 0

q slt rd, rs, rt

● if (rs < rt) rd = 1; else rd = 0;

q slti rt, rs, constant

● if (rs < constant) rt = 1; else rt = 0;

q Use in combination with beq, bne

slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L

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 Branch Instruction Design
q Why not blt, bge, etc?
q Hardware for <, ≥, … slower than =, ≠
● Combining with branch involves more work per instruction,
requiring a slower clock
● All instructions penalized!

q beq and bne are the common case

q This is a good design compromise

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 §2.8 Supporting Procedures in Computer Hardware
Procedure Calling
q Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure s operations
5. Place result in register for caller
6. Return to place of call

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 Procedure Call Instructions
q Procedure call: jump and link

jal ProcedureLabel
● Address of following instruction put in $ra
● Jumps to target address

q Procedure return: jump register

jr $ra
● Copies $ra to program counter
● Can also be used for computed jumps
- e.g., for case/switch statements

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 j

j
j j
j

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 j

j j

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 Target 1, 2, 3, 4, 5, 6, 7, 8
Given 6, 5, 3, 1, 8, 7, 2, 4
i=1 5, 6, 3, 1, 8, 7, 2, 4
i=2 5, 3, 6, 1, 8, 7, 2, 4
3, 5, 6, 1, 8, 7, 2, 4
i=3 3, 5, 1, 6, 8, 7, 2, 4
3, 1, 5, 6, 8, 7, 2, 4
1, 3, 5, 6, 8, 7, 2, 4

i=4 1, 3, 5, 6, 8, 7, 2, 4

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