INTRODUCTION TO VLSI

TESTING

Dr. H. P. Koringa

EC Department
Government Engineering College,
Rajkot-India
WHAT IS THIS CHAPTER ABOUT?

 Introduce fundamental concepts and various

aspects of VLSI testing

 Focus on
 Importance of testing in the design and
manufacturing processes
 Challenges in test generation and fault modeling
 Levels of abstraction in VLSI testing

 Provide overview of VLSI test technology

2
INTRODUCTION TO VLSI TESTING

 Introduction

 Testing During VLSI Life Cycle

 Test Generation

 Fault Models

 Levels of Abstraction

 Overview of Test Technology

 Concluding Remarks

3
 INTRODUCTION
 Integrated Circuits (ICs)
have grown in size and 1.E+09
complexity since the late
1.E+08
1950’s
1.E+07

Number of Transistors
 Small Scale Integration (SSI)
 Medium Scale Integration 1.E+06

(MSI) 1.E+05
 Large Scale Integration (LSI) 1.E+04
 Very Large Scale Integration 1.E+03 VLSI
(VLSI)
1.E+02
 Moore’s Law: scale of ICs S M
LSI
1.E+01
doubles every 18 months S S
1.E+00 I I
 Growing size and complexity
1960s 1970s 1980s 1990s 2000s
poses many and new testing
challenges
4
IMPORTANCE OF TESTING

 Moore’s Law results from decreasing feature

size (dimensions)
 from 10s of m to 10s of nm for transistors and
interconnecting wires
 Operating frequencies have increased from
100KHz to several GHz
 Decreasing feature size increases
probability of defects during manufacturing
process
 A single faulty transistor or wire results in faulty
IC
 Testing required to guarantee fault-free products
5
 IMPORTANCE OF TESTING
 Rule of Ten: cost to detect faulty IC increases by an order
of magnitude as we move from:
 device → PCB → system → field operation
 Testing performed at all of these levels
 Testing also used during
 Manufacturing to improve yield
 Failure mode analysis (FMA)
 Field operation to ensure fault-free system operation
 Initiate repairs when faults are detected

6
TESTING DURING VLSI LIFE CYCLE

 Testing typically consists of

 Applying set of test stimuli to
 Inputs of circuit under test (CUT), and
 Analyzing output responses
 If incorrect (fail), CUT assumed to be faulty
 If correct (pass), CUT assumed to be fault-free

Input1 Output1
Input Circuit Output
Test Under Test Response Pass/Fail
Inputn Outputm
Stimuli (CUT) Analysis
7
TESTING DURING VLSI DEVELOPMENT

 Design verification
Design Specification
targets design errors
 Corrections made
Design Design Verification
prior to fabrication
 Remaining tests
Fabrication Wafer Test
target manufacturing
defects
Packaging Package Test
 A defect is a flaw or
physical imperfection
that can lead to a fault Quality Assurance Final Testing

8
DESIGN VERIFICATION

 Differentlevels of
abstraction during design Design Specification
 CAD tools used to synthesize
design from RTL to physical Behavioral (Architecture) Level
level
 Simulation used at various Register-Transfer Level
level to test for
 Design errors in behavioral Logical (Gate) Level
or RTL
 Design meeting system Physical (Transistor) Level
timing requirements after
synthesis 9
 YIELD AND REJECT RATE
 We expect faulty chips due to manufacturing defects
 Called yield number of acceptable parts
yield =
total number of parts fabricated
 2 types of yield loss
 Catastrophic – due to random defects
 Parametric – due to process variations
 Undesirable results during testing
 Faulty chip appears to be good (passes test)
 Called reject rate
 Good chip appears to be faulty (fails test)
 Due to poorly designed tests or lack of DFT

number of faulty parts passing final test

reject rate =
total number of parts passing final test 10
 ELECTRONIC SYSTEM MANUFACTURING
 A system consists of
 PCBs that consist of
 VLSI devices
 PCB fabrication similar to PCB Fabrication Bare Board Test
VLSI fabrication
 Susceptible to defects PCB Assembly Board Test

 Assembly steps also

susceptible to defects Unit Assembly Unit Test

 Testing performed at all stages

of manufacturing System Assembly System Test

11
 SYSTEM-LEVEL OPERATION
S Normal system operation
1

 Faults occur 0
t0 t1 t2 t3 t4 t
during system operation
failures
 Exponential failure law
 Interval of normal system operation is random number
exponentially distributed
 Reliability
 Probability that system will operate normally until time t
P(Tn  t ) = e − t
 Failure rate, , is sum of individual component failure
rates, i
k
 =  i 12
i =0
 SYSTEM-LEVEL OPERATION
 Mean Time Between Failures 
(MTBF) 1

MTBF = e − t dt =

 Repair time (R) also assumed to 0

obey exponential distribution P( R  t ) = e − t

  is repair rate
1
 Mean Time To Repair (MTTR) MTTR =

 Fraction of time that system is
operating normally called system MTBF
availability system availability =
MTBF + MTTR
 High reliability systems have system
availabilities greater than 0.9999
 Referred to as “four 9s”

13
 SYSTEM-LEVEL TESTING

 Testing required to ensure system availability

 Types of system-level testing
 On-line testing – concurrent with system operation
 Off-line testing – while system (or portion of) is taken out of
service
 Performed periodically during low-demand periods
 Used for diagnosis (identification and location) of faulty replaceable

components to improve repair time

14
 Some Real Defects in Chips
• Processing Faults
– missing contact windows
– parasitic transistors
– oxide breakdown

• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)

• Packaging Failures
– Contact degradation
– Seal leaks

• Time-Dependent Failures
– Dielectric breakdown
– Electromigration
 Defects, Faults, Errors and
Failures
• Defect: An unintended difference between the
implemented hardware and its intended design
• Fault: A representation of a “defect” at abstracted
functional level
– May or may not cause a problem

• Error: Manifestation of a fault that results in incorrect

circuit (system) outputs or states
– Caused by faults

• Failure: Deviation of a circuit or system from its specified

behavior
– Fails to do what it should do
– Caused by an error

• Defect ---> Fault ---> Error ---> Failure

DEFECT, FAULT, AND ERROR
 Example
 Defect: b short to ground
 Fault: signal b stuck-at 0
 Error: a=1, b=1, output c=0 (correct output c=1)
 No Error when a=0 or b=0

a c
b
 WHY MODEL FAULTS ?

 Identifies target faults

 Model faults most likely to occur
 Limits the scope of test generation
 Create tests only for the modeled faults
 Makes analysis possible
 Associate specific defects with specific test patterns
 Makes test effectiveness measurable by
experiments
 Fault coverage can be computed for specific test
patterns to reflect its effectiveness
Fault Models

• Stuck-At Faults
• Bridging/break Faults
• Transistor Stuck-On/Open Faults
• Functional Faults
• Memory Faults
• Delay Faults
• Transition Faults
• State Transition Faults
 Single Stuck-At Faults
Faulty Response
Test Vector
Fault-free Response
0 0

1 1/ 0
1
1/0
1
stuck-at-0

Assumptions:• Only one line is faulty. (Why?)

• Faulty line permanently set to 0 or 1.
• Fault can be at an input or output of
a gate.
 Single Stuck-at Faults
• # single stuck-at fault sites in a Boolean gate
circuit
= #PI + #gates + # (fanout branches)
• Example: A 4-NAND XOR circuit has 12 fault sites
( ) and 24 single stuck-at faults
c
j
a d
g h
z
1 i
b e 1

k How many
f
faults?
 MULTIPLE STUCK-AT FAULTS

 Several stuck-at faults occur at the same time

 Important in high density circuits
 For a circuit with k lines
 There are 2k single stuck-at faults
 There are 3k-1 multiple stuck-at faults
 ATPG algorithms for multiple s-a-faults are
much more complex and not as well developed
 Why Single Stuck-At Faults?
• Complexity is greatly reduced.
Many different physical defects may be modeled by the same
logical single stuck-at fault.
• Single stuck-at fault is technology independent.
Can be applied to TTL, ECL, CMOS, etc.
• Single stuck-at fault is design-style independent.
Gate Arrays, Standard Cell, Custom VLSI
• Even when single stuck-at fault does not accurately
model some physical defects, the tests derived for
these faults may still be effective for these defects.
• Single stuck-at tests cover a large percentage of
multiple stuck-at faults.
TEST GENERATION
 A test is a sequence of test patterns, called test vectors,
applied to the CUT whose outputs are monitored and
analyzed for the correct response
 Exhaustive testing – applying all possible test patterns to
CUT
 Functional testing – testing every truth table entry for a
combinational logic CUT
 Neither of these are practical for large CUTs
 Fault coverage is a quantitative measure of quality of a
set of test vectors

24
FAULT DETECTION

 A test (vector) t detects a fault f iff z( t)  zf (t) = 1

 t detects f <=> z f (t )  z (t )
 Example

X1 Z1
x
s-a-1
X2

Z2
X3

Z1=X1X2 Z2=X2X3

Z1f =X1 Z2f =X2X3

The test 001 detects f because z 1(001)=0 while z1f

(001)=1
SENSITIZATION
 A test t that detects a fault f
 Activates f (or generate a fault effect) by creating
different v and vf values at the site of the fault
 Propagates the error to a primary output w by
making all the lines along at least one path between
the fault site and w have different v and vf values
 A line whose value in the test changes in the
presence of the fault f is said to be sensitized to
the fault f by the test
 A path composed of sensitized lines is called a
sensitized path x1 a
x2 b d g
i y
e f h
x3 c
 DETECTABILITY

 A fault f is said to be detectable if there exists a

test t that detects f ; otherwise, f is an
undetectable fault
 For an undetectable fault f, for all input x
zf ( x) = z( x)

 No test can simultaneously activate f and

create a sensitized path to a primary output
UNDETECTABLE FAULT

1
a
G1 1/0
1

s-a-0
b 0 x
z
0 0

???
c
1

 G1 output stuck-at-0 fault is undetectable

 Undetectable faults do not change the function of
circuit
 The related circuit can be deleted to simplify the
circuit
UNDETECTABLE FAULT
 The presence of an undetectable fault f may
prevent the detection of another fault g, even
when there exists a test which detects the fault g.
 Example:
 A detectable fault a s-a-0 becomes undetectable under
the presence of a undetectable fault c s-a-1.

a s.a.0 In fact, Z = AB + ABC = AB

A Thus the circuit can be simplified.
B
In general, identifying undetectable
Z faults can lead to simplication of
CUT
C
c s.a.1
TEST SET

 Complete detection test set: A set of tests that

detect any detectable faults in a class
of faults
 The quality of a test set is measured by fault
coverage
 Fault coverage: Fraction of faults that are
detected by a test set
 The fault coverage can be determined by fault
simulation
 >95% is typically required for single stuck-at fault
model
in a complex system such as a CPU
FAULT EQUIVALENCE

 A test t distinguishes between faults  and  if

z (t)  z (t)

 Two faults,  &  are said to be equivalent

in a circuit , iff the function under  is equal to
the function under  for any input combination
(sequence) of the circuit.
 z (t ) = z (t )for all t
 No test can distinguish between  and 
 Any test which detects one of them detects both
faults
FAULT EQUIVALENCE
 AND gate: all s-a-0 faults are equivalent
 OR gate: all s-a-1 faults are equivalent

 NAND gate: all the input s-a-0 faults and the output
s-a-1 faults are equivalent
 NOR gate: all input s-a-1 faults and the output
s-a-0 faults are equivalent
 Inverter: input s-a-1 and output s-a-0 are equivalent
input s-a-0 and output s-a-1 are equivalent

s.a.0
s.a.1
s.a.1
Example: Three faults shown
are equivalent
 EQUIVALENCE EXAMPLE

sa0 sa1
Faults in red
sa0 sa1 removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32
 TEST GENERATION

 Fault coverage for a given set of test vectors

number of detected faults
fault coverage =
total number of faults

 100% fault coverage may be impossible due to

undetectable faults
number of detected faults
fault detection efficiency =
total number of faults − number of undetectable faults

 Reject rate = 1 – yield(1 – fault coverage)

 A PCB with 40 chips, each with 90% fault coverage and
90% yield, has a reject rate of 41.9%
 Or 419,000 defective parts per million (PPM) 34
TEST GENERATION

 Goal: find efficient set of test vectors with maximum

fault coverage
 Fault simulation used to determine fault coverage
 Requires fault models to emulate behavior of defects
 A good fault model:
 Is computationally efficient for simulation
 Accurately reflects behavior of defects
 No single fault model works for all possible defects

35
FAULT MODELS
A given fault model has k types of faults
 k = 2 for most fault models
A given circuit has n possible fault sites
 Multiple fault model –circuit can have
multiple faults (including single faults
 Number of multiple fault = (k+1)n-1
 Each fault site can have 1-of-k fault types or be fault-free
 The “-1” represents the fault-free circuit

 Impractical for anything but very small circuits

 Single fault model – circuit has only 1 fault
 Number of single faults = k×n
 Good single fault coverage generally implies good
multiple fault coverage 36
FAULT MODELS
 Equivalent faults
 One or more single faults that have identical behavior for
all possible input patterns
 Only one fault from a set of equivalent faults needs to be
simulated
 Fault collapsing
 Removing equivalent faults
 Except for one to be simulated
 Reduces total number of faults
 Reduces fault simulation time
 Reduces test pattern generation time

37
 STUCK-AT FAULTS
Truth table for fault-free behavior
❑ Any line can be and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
▪ Stuck-at-0 (SA0) y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
▪ Stuck-at-1 (SA1) a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
# fault types: k=2 b SA1 0 0 0 0 1 1 1 1

❑ Example circuit: c SA0 0 0 0 0 0 0 1 1

c SA1 1 1 0 0 1 1 1 1
d SA0 0 1 0 0 0 1 0 0
▪ # fault sites: n=9 d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
▪ # single faults =2×9=18 e SA1 0 0 0 0 0 0 1 1
f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
38
 STUCK-AT FAULTS
Truth table for fault-free behavior
❑ Valid test vectors and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
▪ Faulty circuit differs y 0 1 0 0 0 1 1 1
from good circuit a SA0 0 1 0 0 0 1 0 0
a SA1 0 1 1 1 0 1 1 1
▪ Necessary vectors: b SA0 0 1 0 1 0 1 0 1
b SA1 0 0 0 0 1 1 1 1
011 detects f SA1, e SA0 c SA0 0 0 0 0 0 0 1 1
100 detects d SA1 c
d
SA1
SA0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
1
0
– Detect total of 10 faults d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
– 001 and 110 detect e SA1 0 0 0 0 0 0 1 1
remaining 8 faults f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1

x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
39
 STUCK-AT FAULTS
Truth table for fault-free behavior
❑4 sets of equivalent and behavior of all possible stuck-at faults

faults x1x2x3
y
000 001 010 011 100 101 110
0 1 0 0 0 1 1
111
1

❑ # collapsed faults = a
a
SA0
SA1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
2×(PO+FO)+GI-NI b
b
SA0
SA1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
▪ PO= # primary outputs c
c
SA0
SA1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
▪ FO= # fanout stems d
d
SA0
SA1
0
0
1
1
0
0
0
0
0
1
1
1
0
1
0
1
▪ GI= # gate inputs e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
▪ NI= # inverters f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1

x2 b d g
g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
40
STUCK-AT FAULTS

 # collapsed faults = 2×(PO+FO)+GI-NI

 PO= number of primary outputs
 FO= number of fanout stems
 GI= total number of gate inputs
for all gates including inverters
 NI= total number of inverters
 For example circuit, # collapsed faults = 10
 PO= 1, FO= 1, GI= 7, and NI= 1
 Fault collapsing typically reduces number of stuck-at
faults by 50% - 60%

41
TRANSISTOR FAULTS VDD
A
P1
2-input
 Any transistor can be CMOS B P2
NOR Z
 Stuck-short gate
 Also known as stuck-short N1 N2

 Stuck-open
 Also known as stuck-open VSS
# fault types: k=2 Truth table for fault-free circuit
and all possible transistor faults
 Example circuit AB 00 01 10 11
 # fault sites: n=4 Z 1 0 0 0
N1 stuck-open 1 0 last Z 0
 # single faults =2×4=8
N1 stuck-short IDDQ 0 0 0
N2 stuck-open 1 last Z 0 0
N2 stuck-short IDDQ 0 0 0
P1 stuck-open last Z 0 0 0
P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0 42
P2 stuck-short 1 IDDQ 0 0
 TRANSISTOR FAULTS VDD
A
P1
 Stuck-short faults cause 2-input
B
conducting path from VDD to VSS CMOS P2
Z
NOR
 Can be detect by monitoring steady- gate
state power supply current IDDQ N1 N2

 Stuck-open faults cause output

node to store last voltage level VSS
Truth table for fault-free circuit
 Requires sequence of 2 vectors for and all possible transistor faults
detection AB 00 01 10 11
 00→10 detects N1 stuck-open Z 1 0 0 0
N1 stuck-open 1 0 last Z 0
N1 stuck-short IDDQ 0 0 0
N2 stuck-open 1 last Z 0 0
N2 stuck-short IDDQ 0 0 0
P1 stuck-open last Z 0 0 0
P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0 43
P2 stuck-short 1 IDDQ 0 0
TRANSISTOR FAULTS
 # collapsed faults = 2×T -TS+GS -TP+GP
 T = number of transistors
 TS= number of series transistors
 GS= number of groups of series transistors
 TP= number of parallel transistors
 GP= number of groups of parallel transistors
 For example circuit, # collapsed faults = 6
 T=4, TS= 2, GS= 1, TP= 2, & GP= 1
 Fault collapsing typically reduces number of transistor
faults by 25% to 35%

44
SHORTS AND OPENS

 Wires can be
 Open
 Opens in wires interconnecting transistors to form gates behave
like transistor stuck-open faults
 Opens in wires interconnecting gates to form circuit behave like

stuck-at faults
 Opens are detected by vectors detecting transistor and stuck-at

faults
 Short to an adjacent wire
 Also known as a bridging fault

45
EXAMPLES OF SHORT AND OPEN FAULTS

46
BRIDGING FAULTS AS AD
source destination
 Three different models BS BD
bridging fault
 Wired-AND/OR AS AD AS AD
 Dominant
 Dominant-AND/OR BS B D BS BD
Wired-AND Wired-OR
 Detectable by IDDQ testing AS AD AS AD

AS BS 0 0 0 1 1 0 1 1 BS BD BS BD
AD BD 0 0 0 1 1 0 1 1 A dominates B B dominates A
Wired-AND 0 0 0 0 0 0 1 1 AS AD AS AD
Wired-OR 0 0 1 1 1 1 1 1
A dominates B 0 0 0 0 1 1 1 1 BS BD BS BD
B dominates A 0 0 1 1 0 0 1 1 A dominant-AND B A dominant-OR B
A dominant-AND B 0 0 0 0 1 0 1 1 AS AD AS AD
B dominant-AND A 0 0 0 1 0 0 1 1
A dominant-OR B 0 0 0 1 1 1 1 1 BS BD BS 47 BD
B dominant-OR A 0 0 1 1 1 0 1 1 B dominant-AND A B dominant-OR A
DELAY FAULTS AND CROSSTALK
 Path-delay fault model considers cumulative
propagation delay through CUT
 2 test vectors create transition along path
 Faulty circuit has excessive delay
 Delays and glitches can be caused by crosstalk between
interconnect
 due to inductance and capacitive coupling

0 0 x1
0 1 x2 3

t=0 t=7
2 y
v2 v1
t=2
2 48
1 1 x3 3
PATTERN SENSITIVITY AND COUPLING
FAULTS
 Common in high density RAMs
 Pattern sensitivity fault
 Contents of memory cell is affected by contents of
neighboring cells
 Coupling fault
 Transition in contents of one memory cell causes change
in contents of another cell

49
ANALOG FAULT MODELS

 Catastrophic faults
 Shorts and opens
 Parametric faults
 Parametric variations in passive and active components
cause components to be out of tolerance range
 Active components can sustain defects that affect
DC and/or AC operation

50
 LEVELS OF ABSTRACTION
 High levels have few implementation details needed for
effective test generation
 Fault models based on gate & physical levels
 Example: two circuits for same specification
 Ckt B test vectors do not detect 4 faults in Ckt A

a SA1
f(a,b,c)=m(1,7)+d(3) = abc + abc + Xabc b
c
ab 0 0 0 1 1 1 1 0 SA1 f
c f = abc + abc
0 1 X SA1 Circuit A
Circuit A Test Vectors
1 1 {111,110,101,011,010,000} SA1

ab 0 0 0 1 1 1 1 0 a
c
1 X f = ab + bc b Circuit B
0
Circuit B Test Vectors f51
1 1 {111,101,010,000}
c
OVERVIEW OF VLSI TEST TECHNOLOGY

 Automatic Test Equipment (ATE) consists of

 Computer – for central control and flexible test &
measurement for different products
 Pin electronics & fixtures – to apply test patterns to
pins & sample responses
 Test program – controls timing of test patterns &
compares response to known good responses

52
OVERVIEW OF VLSI TEST TECHNOLOGY
 Automatic Test Pattern Generation (ATPG)
 Algorithms generating sequence of test vectors for a given
circuit based on specific fault models
 Fault simulation
 Emulates fault models in CUT and applies test vectors to
determine fault coverage
 Simulation time (significant due to large number of faults to
emulate) can be reduced by
 Parallel, deductive, and concurrent fault simulation

53
OVERVIEW OF VLSI TEST TECHNOLOGY

 Design for Testability (DFT)

 Generally incorporated in design
 Goal: improve controllability and/or observability of
internal nodes of a chip or PCB
 Three basic approaches
 Ad-hoc techniques
 Scan design
 Boundary Scan
 Built-In Self-Test (BIST)

54
DESIGN OF TESTABILITY
 Ad-hoc DFT techniques
 Add internal test points (usually multiplexers) for
 Controllability
 Observability

 Added on a case-by-case basis

 Primarily targets “hard to test” portions of chip

Normal system Normal system

data 0 data 0
Internal Primary
Test data input node to be Internal node to output
1 be observed 1
controlled
Test mode select Test mode select
55
controllability test point observability test point
DESIGN FOR TESTABILITY
Primary Primary
 Scan design Inputs Combinational Outputs
Logic
 Transforms flip-flops of chip into
a shift register
 Scan mode facilitates FFs
 Shifting in test vectors 1
Di
 Shifting out responses Di Qi 0 Qi
FF 1 FF
 Good CAD tool support 2
Qi-1
Clk Scan Clk
 Transforming flip-flops to shift Mode
register 3

 ATPG Primary Primary

Inputs Combinational Outputs
Logic
Scan
Data
FFs 56Out

Scan Data In
 DESIGN FOR TESTABILITY
 Boundary Scan – scan design applied to I/O buffers of
chip
 Used for testing interconnect on PCB
 Provides access to internal DFT capabilities
 IEEE standard 4-wire Test Access Port (TAP)

tri-state control Control TAP pin I/O Function

from IC BS Cell TCK input Test clock
Scan Out
TMS input Test Mode Select
Input Output BS Cell TDI input Test Data In
0 Output TDO output Test Data Out
0 1
Scan capture update Pad
1
In FF FF
Shift
input data Input 57
Capture Update
to IC BS Cell
DESIGN FOR TESTABILITY
 Built-In Self-Test (BIST)
 Incorporates test pattern generator (TPG) and output
response analyzer (ORA) internal to design
 Chip can test itself
 Can be used at all levels of testing
 Device → PCB → system → field operation

Primary Inputs
0 Circuit Primary Outputs
Under
TPG 1 Test
Pass
BIST Mode ORA 58
Fail
 DEFINITIONS
 Design synthesis: Given an I/O function, develop a
procedure to manufacture a device using known materials
and processes.

59
 Verification: Predictive analysis to ensure that the
synthesized design, when manufactured, will perform the
given I/O function.
 Test: A manufacturing step that ensures that the physical
device, manufactured from the synthesized design, has no
manufacturing defect.
 VERIFICATION VS. TEST

 Verifies correctness of  Verifies correctness of

design. manufactured hardware.
 Performed by  Two-part process:
simulation, hardware  1. Test generation: software
emulation, or formal process executed once during
methods. design
 Performed once prior to
 2. Test application: electrical
tests applied to hardware
manufacturing.
 Test application performed on
 Responsible for quality
every manufactured device.
of design.
 Responsible for quality of
devices. 60
CONCLUDING REMARKS

Many new testing challenges

presented by
 Increasing complexity of VLSI
devices
 Decreasing feature size
This chapter presented
introduction to VLSI testing
Remaining chapters present
more details as well as
solutions to these challenges
61
Q?