ECE514 – Advanced Topics In Electronics
QUESTION 1 :
Draw a logic diagram that implements the expression A(B+C)(C’+D)(B+D’) directly
(do not simplify first), using only simple gates.
B
C
D A
QUESTION 2:
Draw a circuit that implements the VHDL code fragment shown below. Assume that x
and z are two bit signals. All others are of type std_logic. You may use simple gates,
multiplexors and flip flops in your circuit diagram.
with z select
x <= a & b when “00” | “01”,
“01” when “10”,
“11” when others;
process (clk) begin
if rising_edge(clk) then
if a > b then
y <= a and c;
elsif a /= c then
y <= x(0);
end if; 1
end if; D
end process; x(0) 1 0
0 >C
2
0
clk
y
1 2
x
01 2
11 3
2
A z
B
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QUESTION 3 :
Draw a diagram of an 8-to-1 multiplexor with data inputs D0 to D7 and a 3 bit control input C,
using smaller multiplexors as building blocks. Make sure that the all signals and mux inputs are
labeled appropriately. Pay special attention to the control inputs of the mux components in your
circuit.
D0 0
D1 1
D2 2
D3 3
0
D4 1
0
D5 1 C(2)
D6
2
D7 3
C(1..0)
How many LUT4s does it take to implement this circuit?
It takes 3 LUTs to implement each 4:1 mux, plus one more to implement the 2:1 mux, so 7 in all.
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QUESTION 4:
VHDL divides the description of a module into an Entity and an Architecture section.
A. What is the purpose of each of these two sections?
The Entity section specifies the name of the entity as well as the names and types of
its input and output ports.
The Architecture section specifies the name of this architecture for a specific entity
and then contains either a structural or behavioral description of the entity.
Essentially, the Entity section specifies the interface to the entity and the Architecture
section specifies the functionality or composition of the entity.
B. Would it ever make sense to have multiple alternative Architecture
sections for a single Entity section? Explain.
Yes. A behavioral description might specify the functionality of the entity for
simulation purposes, whereas a structural description might specify the composition of the
entity in terms of lower-level components for documentation purposes. Or alternative
behavioral descriptions might be written to explore tradeoffs between functionality and
chip area.
C. What is a STD_LOGIC type?
VHDL uses the STD_LOGIC type to model represent logic values. It includes not only
values of 0 and 1, but also Z, U, X, –, L, W, and H which are needed for some designs.
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QUESTION 5:
1) Modify the following VHDL model by adding an enable input. When enable = ‘0’, the outputs are set to
“ZZZZ’ and as specified when enable = ‘1’. Further, translate the process into concurrent signal assignment
statements that include the new functionality.
library ieee;
use ieee.std_logic_1164.all;
entity TWO_TO_4_DEC is generic(DEL: TIME);
port(I: in std_logic_vector(1 downto 0);
EN : in std_logic;
O: out std_logic_vector(3 downto 0));
end TWO_TO_4_DEC;
architecture ALG of TWO_TO_4_DEC is begin
process(I) begin
if (EN = ꞌ0ꞌ) then O <= "ZZZZ";
elsif(EN = ꞌ1ꞌ) then case I is
when "00" => O<= "0001" after DEL; when "01" => O<= "0010" after DEL; when "10" => O<= "0100" after
DEL; when "11" => O<= "1000" after DEL;
end case; end if;
end process; end ALG;
2) Construct an 8 bit ALU using two 4- bit ALUs (entity shown below).
A. (4 points) Entity
B. (8 points) Architecture
library ieee;
use ieee.std_logic_1164.all; entity ALU is
generic(DEL: TIME);
port(A,B: in std_logic_vector(3 downto 0); CI: in std_logic; FSEL: in std_logic_vector(1 downto 0);
F: out std_logic_vector(3 downto 0); COUT: out std_logic);
end ALU;
library ieee;
use ieee.std_logic_1164.all; entity ALU8 is
generic (DEL : TIME);
port (A, B : in std_logic_vector(7 downto 0); CI : in std_logic; FSEL : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0); COUT : out std_logic); end ALU8;
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architecture ALU8 of ALU8 is signal TEMP : std_logic;
begin
U0 : entity work.ALU generic map (DEL)
port map (A => A(3 downto 0), B => B(3 downto 0), CI => CI, FSEL => FSEL, F => F(3 downto 0), COUT =>
TEMP);
U1 : entity work.ALU generic map (DEL)
port map (A => A(7 downto 4), B => B(7 downto 4), CI => TEMP, FSEL => FSEL, F => F(7 downto 4), COUT
=> COUT);
end ALU8;
QUESTION 6:
Binary counter: Write a VDHL code for binary up/down counter. It must have an asynchronous reset to
initialize it to 0. In addition, the range of the counter and whether it is counting up or down must be
parameterized. It must have two outputs: one indicating current counting value (count) and another output (z)
that must be asserted when the counter reaches its upper or lower limit. Ensure that no latch is inferred for z.
When the counter reaches this limit, it must wrap around and the next value will be zero.
entity updown is
generic(n:integer:=4; up:integer:=-1); port(clk, reset: in std_logic;
count: out integer range -n+1 to n-1; z: out std_logic); end entity updown;
architecture beh of updown is begin
process(clk, reset)
variable cnt: integer range -n+1 to n-1; begin
z <= '0';
if reset = '1' then cnt := 0;
elsif(rising_edge(clk)) then
if cnt = n-1 then cnt := 0; z <= '1'; elsif cnt = -n+1 then cnt := 0; z <= '1'; else cnt := cnt + up;
end if; end if;
count <= cnt; end process;
end architecture beh;
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QUESTION 7:
Read each question carefully and select the CORRECT answer from the given options.
1) Which programming language served as the foundation for VHDL's development?
a. C language
b. Python
c. ADA language
d. Java
2) What is NOT listed as one of the main applications of HDL?
a. Converting between abstraction levels
b. Circuit synthesis
c. Operating system development
d. Design verification
3) Which of the following is a valid scalar data type in VHDL?
A. array
B. vector
C. boolean
D. string
4) Which package inclusion is necessary to use std_logic data types?
A. use IEEE.std_logic_1164.all
B. library std_logic_1164
C. use IEEE.std_logic.all
D. include IEEE.std_logic
5) Which of the following correctly represents strongly-driven values in std_logic?
A. 'L' and 'H'
B. 'Z' and 'W'
C. '0' and '1'
D. 'U' and 'X'
6) What is the meaning of 'W' in std_logic data type?
A. Strong driven unknown
B. Weak driven unknown
C. High impedance
D. Don't care
7) What is the primary purpose of an entity in VHDL?
a. To implement behavioral logic
b. To declare the interface and specify input/output ports
c. To contain sequential statements
d. To define signal arrays
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8) Which of the following is a valid Aggregate data type in VHDL?
A. array
B. bit-vector
C. boolean
D. string
9) Which package inclusion is necessary to use std_logic data types?
A. use IEEE.std_logic_1164.all
B. library std_logic_1164
C. use IEEE.std_logic.all
D. include IEEE.std_logic
10) Which statement about VHDL data types is correct?
a. VHDL only supports binary data types
b. Integer is not a supported data type in VHDL
c. std_logic is a commonly used data type for signal values
d. Data types cannot be used with arrays
11) Which of the following represents the correct format for a simple signal assignment in
VHDL?
A.signal_name=>expression;
B.signal_name:=expression;
C. signal_name <= expression; D. signal_name -> expression;
12) In VHDL operators, which category does the '&' symbol belong to?
A. Logical operators
B. Addition & Concatenation operators
C. Relational operators
D. Multiplying operators
13) Which package contains the built-in data types (BIT, BOOLEAN, INTEGER) in VHDL?
A.IEEE
B.WORK
C.Standard
D. NUMERIC
14) Within a single process in VHDL architecture, how are statements executed?
A. In parallel with other statements
B. Based on signal priorities
C. Sequentially in order
D. Randomly based on system clock
15) How does the architecture describe the overall design?
A. It describes only the timing requirements
B. It describes only the signal connections
C. It describes the functionality of the design
D. It describes only the process hierarchy
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16) Which IEEE library package is specifically mentioned as containing operator overloading
functions?
A. std_logic_vectors
B. std_logic_unsigned
C. std_logic_arithmetic
D. std_logic_operations
QUESTION 8 :
1) The VHDL code uses the IEEE libraries std_logic_1164 and std_logic_unsigned.( T ).
2) The entity 'count_a' declares three input ports (clk, rst, updn) and one output port (q).( T ) .
3) The process in the architecture is sensitive to both rst and clk signals.( T ).
4) A variable inside a VHDL process updates its value immediately upon assignment.( T ).
5) Counters in VHDL are accumulators that always add or subtract 1 as shown in the code.( T ).
6) When the 'updn' signal is '1', the variable tmp_q is incremented by 1 on the rising edge of clk.( T ).
7) If the 'updn' signal is not '1', the variable tmp_q is decremented by 1 on the rising edge of clk.( T ).
8) The asynchronous reset is activated when rst is '1', setting tmp_q to all zeros.( F ).
9) The output signal q is assigned the current value of the variable tmp_q at the end of each process
execution.( T ).
10 ) The given example indicates that the counter implementation requires 17 LEs.( T ).
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