Lecture 23
Design for Testability
(DFT): Full-Scan
(Lecture 19alt in the Alternative Sequence)
Definition
Ad-hoc methods
Scan design
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Design rules
Scan register
Scan flip-flops
Scan test sequences
Overheads
Scan design system
Summary
VLSI Test: Lecture 23
Definition
Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
DFT methods for digital circuits:
Ad-hoc methods
Structured methods:
Scan
Partial Scan
Built-in self-test (BIST)
Boundary scan
DFT method for mixed-signal circuits:
Analog test bus
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VLSI Test: Lecture 23
Ad-Hoc DFT Methods
Good design practices learnt through experience are
used as guidelines:
Avoid asynchronous (unclocked) feedback.
Make flip-flops initializable.
Avoid redundant gates. Avoid large fanin gates.
Provide test control for difficult-to-control signals.
Avoid gated clocks.
Consider ATE requirements (tristates, etc.)
Design reviews conducted by experts or design auditing
tools.
Disadvantages of ad-hoc DFT methods:
Experts and tools not always available.
Test generation is often manual with no guarantee of
high fault coverage.
Design iterations may be necessary.
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VLSI Test: Lecture 23
Scan Design
Circuit is designed using pre-specified design
rules.
Test structure (hardware) is added to the
verified design:
Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing
test.
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VLSI Test: Lecture 23
Scan Design Rules
Use only clocked D-type of flip-flops for all
state variables.
At least one PI pin must be available for test;
more pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.
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VLSI Test: Lecture 23
Correcting a Rule
Violation
All clocks must be controlled from PIs.
Comb.
logic D1
Q
Comb.
logic
FF
D2
CK
Comb.
logic
D1
D2
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CK
VLSI Test: Lecture 23
Q
FF
Comb.
logic
Scan Flip-Flop (SFF)
Master latch
Slave latch
TC
Q
Logic
overhead
MUX
SD
CK
D flip-flop
CK
TC
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Master open Slave open
Normal mode, D selected
t
Scan mode, SD selected
VLSI Test: Lecture 23
Level-Sensitive ScanDesign Flip-Flop (LSSDSFF)
Master latch
Slave latch
D
Q
MCK
Q
D flip-flop
SD
MCK
Logic
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overhead
MCK
TCK
Scan
mode
TCK
TCK
Normal
mode
SCK
SCK
VLSI Test: Lecture 23
Adding Scan Structure
PI
PO
Combinational
SFF
logic
SFF
SCANOUT
SFF
TC or TCK
SCANIN
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Not shown: CK or
MCK/SCK feed all
SFFs.
VLSI Test: Lecture 23
Comb. Test Vectors
PI
I1
I2
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O2
Combinational
SCANIN
TC
Present
state
O1
SCANOUT
logic
S1
S2
VLSI Test: Lecture 23
PO
N1
N2
Next
state
10
Comb. Test Vectors
SCANIN
I2
I1
PI
S1
Dont care
or random
bits
S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
PO
SCANOUT
O2
O1
N1
N2
Sequence length = (ncomb + 1) nsff + ncomb clock periods
ncomb = number of combinational vectors
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nsff = number of scan flip-flops
VLSI Test: Lecture 23
11
Testing Scan Register
Scan register must be tested prior to
application of scan test sequences.
A shift sequence 00110011 . . . of length
nsff+4 in scan mode (TC=0) produces 00, 01,
11 and 10 transitions in all flip-flops and
observes the result at SCANOUT output.
Total scan test length:
(ncomb
+ 2) nsff + ncomb + 4 clock periods.
Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 10 6 clocks.
Multiple scan registers reduce test length.
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VLSI Test: Lecture 23
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Multiple Scan
Registers
Scan flip-flops can be distributed among
any number of shift registers, each having a
separate scanin and scanout pin.
Test sequence length is determined by the
longest scan shift register.
Just one test control (TC) pin is essential.
PI/SCANIN
Combinational
logic
SFF
SFF
M
U
X
PO/
SCANOUT
SFF
TC
CK
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Scan Overheads
IO pins: One pin necessary.
Area overhead:
Gate overhead = [4 nsff/(ng+10nsff)] x 100%,
where ng = comb. gates; nff = flip-flops;
Example ng = 100k gates, nsff = 2k flipflops, overhead = 6.7%.
More accurate estimate must consider scan
wiring and layout area.
Performance overhead:
Multiplexer delay added in combinational
path; approx. two gate-delays.
Flip-flop output loading due to one additional
fanout; approx. 5-6%.
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Hierarchical Scan
Scan flip-flops are chained within
subnetworks before chaining subnetworks.
Advantages:
Scanin
Automatic scan insertion in netlist
Circuit hierarchy preserved helps in
debugging and design changes
Disadvantage: Non-optimum chip layout.
SFF4
SFF1
Scanout
SFF1
Scanin
SFF2
SFF3
Scanout
SFF4
Hierarchical netlist
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SFF3
VLSI Test: Lecture 23
SFF2
Flat layout
15
Optimum Scan Layout
X
X
IO
pad
Flipflop
cell
SFF
cell
SCANIN
TC
Routing
channels
Interconnects
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SCAN
OUT
Active areas: XY and XY
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Scan Area Overhead
Linear dimensions of active area:
X = (C + S) / r
X = (C + S + S) / r
Y = Y + ry = Y + Y(1 ) / T
Area overhead
XY XY
= 100%
XY
1
= [(1+s)(1+ ) 1] x 100%
T
1
= ( s +
T
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y = track dimension, wire
width+separation
C = total comb. cell width
S = total non-scan FF cell
width
s = fractional FF cell area
= S/(C+S)
= SFF cell width fractional
increase
r = number of cell rows
or routing channels
= routing fraction in active
area
T = cell height in track
dimension y
) x 100%
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Example: Scan Layout
2,000-gate CMOS chip
Fractional area under flip-flop cells, s = 0.478
Scan flip-flop (SFF) cell width increase, = 0.25
Routing area fraction, = 0.471
Cell height in routing tracks, T = 10
Calculated overhead = 17.24%
Actual measured data:
Scan implementation
Area overhead
Normalized clock rate
______________________________________________________________________
None
0.0
1.00
Hierarchical
16.93%
0.87
Optimum layout
11.90%
0.91
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VLSI Test: Lecture 23
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ATPG Example: S5378
Original
Number of combinational gates
Number of non-scan flip-flops (10 gates each)
Number of scan flip-flops (14 gates each)
Gate overhead
Number of faults
PI/PO for ATPG
Fault coverage
Fault efficiency
CPU time on SUN Ultra II, 200MHz processor
Number of ATPG vectors
Scan sequence length
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VLSI Test: Lecture 23
2,781
179
0
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414
Full-scan
2,781
0
179
15.66%
4,603
214/228
99.1%
100.0%
5s
585
105,662
19
Automated Scan
Design
Rule
violations
Behavior, RTL, and logic
Design and verification
Scan design
rule audits
Gate-level
netlist
Combinational
ATPG
Scan hardware
insertion
Scan
netlist
Combinational
vectors
Scan sequence
and test program
generation
Test program
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Scan chain order
Design and test
data for
manufacturing
VLSI Test: Lecture 23
Chip layout: Scanchain optimization,
timing verification
Mask data
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Timing and Power
Small delays in scan path and clock skew
can cause race condition.
Large delays in scan path require slower
scan clock.
Dynamic multiplexers: Skew between TC
and TC signals can cause momentary
shorting of D and SD inputs.
Random signal activity in combinational
circuit during scan can cause excessive
power dissipation.
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Summary
Scan is the most popular DFT technique:
Advantages:
Rule-based design
Automated DFT hardware insertion
Combinational ATPG
Design automation
High fault coverage; helpful in diagnosis
Hierarchical scan-testable modules are easily
combined into large scan-testable systems
Moderate area (~10%) and speed (~5%) overheads
Disadvantages:
Large test data volume and long test time
Basically a slow speed (DC) test
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