Microprocessor Systems

Basic Course Outline:

• Register transfer and micro-operations
• Basic computer organization, design, & programming
• Central Processing Unit (CPU)
• 8051 microcontroller assembly + peripheral interfacing
• PIC18 microcontroller using C only

Dr. Memoon Sajid

Assistant Professor
Faculty of Electrical Engineering
GIK Institute of Engineering Sciences and Technology
Phone # +923468710421
Email : [email protected]
Office Hours: As displayed on door
Basic Computer Instructions
Memory Reference Instructions
Input/output Instructions
Complete Computer Description
Design and Control
Control of Registers
Control of Memory
Control of Common BUS
 CONTROL OF COMMON BUS
None
AR
PC
Control DR
AC
Circuitry IR
TR
Mem

X0
1
0
0
0
0
0
0
0

105
 CONTROL OF COMMON BUS

Note: X0 is not X0
included in any 1
0
Selection line (S2, 0
0
s1, S0), so we can 0
0
ignore it 0
0

S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
ENCODER AND MUX NOT REALLY NEEDED, CAN DIRECTLY USE X 0-X7 FROM CONTROL UNIT FOR DECODER BASED BUS CONTROLLER
Design of Accumulator Logic
 DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC
16
16 Adder and 16
From DR logic 16 AC
8 circuit To bus
From INPR
LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR LD
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left CLR
rB11 : AC  0 Clear INR
rB5 : AC  AC + 1 Increment 115
 Lecture 12
Revision of Basic Computer Design
• The author has suddenly
reversed the convention
previously developed. To
avoid confusion, follow
the older one
CENTRAL
CONTROL
UNIT
CENTRAL
CONTROL
UNIT
 Mechanism
• Inputs of all SFRs are connected to the BUS
• Data from the BUS is loaded into a register when the
load input of the desired register is 1
• Data from a register is read and loaded onto the BUS
when the specific register is selected using the
common BUS control unit
• When data has to be shifted from one register to
another
– The source register is selected using BUS control loading its
data on to the BUS
– And at the same time, load input of the destination register
is set to 1 loading the data from the BUS into the register
 SFRs Read/Write Example

=1

A B
Bus selection bit S = 1 (Select B
register that is source)
At the same time, set LD A to 1 =1
Decoder
* At the beginning of the clock
=1
cycle, B’s data is loaded onto the
BUS and at the end, into reg A
Loading data into AR from the BUS
 Key Points
• Memory DOES HAVE a direct connection to the
BUS but NOT with AC (Accumulator)
• For a micro-operation involving ALU on a data
from a memory location, the data is always first
sent to the data register DR
• The operation is performed on DR and AC both
connected to the ALU (processor)
• Other than that, data from any memory location
CAN be transferred anywhere else (IR, AR, DR,
etc.)
Write = RT1 + (D3+D5)T4 + D6T6
 CONTROL OF COMMON BUS
None
AR
PC
Control DR
AC
Circuitry IR
TR
Mem

X0
1
0
0
0
0
0
0
0

105
 CONTROL OF COMMON BUS

Note: X0 is not X0
included in any 1
0
Selection line (S2, 0
0
s1, S0), so we can 0
0
ignore it 0
0

S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
ENCODER AND MUX NOT REALLY NEEDED, CAN DIRECTLY USE X 0-X7 FROM CONTROL UNIT FOR DECODER BASED BUS CONTROLLER
 SFRs Read/Write Example

=1

A B
Bus selection bit S = 1 (Select B
register that is source)
At the same time, set LD A to 1 =1
Decoder
* At the beginning of the clock
=1
cycle, B’s data is loaded onto the
BUS and at the end, into reg A
This expression is same to that of a memory read
 Memory Read/Write

SAME

Decoder

There is a mistake with the write operation, redraw the complete correct circuit as assignment
 BUS and Memory Control
We want M[B] <- M[A] (A to B)
M[AR] <- M[AR] Doesn’t exist
in given instruction set
Have to use 2 commands:
Load M[AR] in to AC using DR
& then store AC to M[AR]
Step-by-Step Execution:
LDA (Load) X7 = 1
D2T4: DR <- M[AR]
D2T5: AC <- DR
STA (Store)
D3T4: M[AR] <- AC
1. M[AR] is source, so memory
is selected by BUS X7=1
2. Memory Read will be 1
3. Load of DR = 1
4. DR is source & is directly
connected to AC (no BUS)
5. Load of AC = 1 B=1 A=1
6. Then AC is source. BUS X4=1
7. Then Memory Write = 1 S=0 S=1
 DESIGN OF ACCUMULATOR LOGIC
Circuits associated with AC
16
16 Adder and 16
From DR logic 16 AC
8 circuit To bus
From INPR
LD INR CLR Clock

Control
gates

All the statements that change the content of AC

D0T5: AC  AC  DR AND with DR
D1T5: AC  AC + DR Add with DR
D2T5: AC  DR Transfer from DR
pB11: AC(0-7)  INPR Transfer from INPR LD
rB9: AC  AC Complement
rB7 : AC  shr AC, AC(15)  E Shift right
rB6 : AC  shl AC, AC(0)  E Shift left CLR
rB11 : AC  0 Clear INR
rB5 : AC  AC + 1 Increment 115
 Timing and Control
+
Instruction Execution
CENTRAL
CONTROL
UNIT
 Increment the data on memory location 50H and store
it on memory location 60H

• Three commands will be used

– AC ← M[50H] ; LDA (Load memory into AC)
– AC ← AC+1 ; INC (Increment AC)
– M[60H] ← AC ; STA(Store AC to Memory)
• Before every command, fetch and decode cycle
will be executed
– R’T0: AR ← PC
– R’T1: IR ← M[AR], PC ← PC+1
– R’T2: Decode. AR ← IR(0-11), (D0-D7) ← IR(12-14)
 Increment the data on memory location 50H and store
it on memory location 60H

• LDA
– D2T4: DR ← M[50H]
– D2T5: AC ← DR, SC ← 0
– IR = 0,010,0000,0101,0000 (I’D2,50H)
• Memory is source, so memory read should be 1 and X7
should be 1 to select memory through BUS control
• DR is destination, so Load input of DR should be 1
• Then AC is destination, so Load input of AC should be 1
• The op-code D2 defines that data of DR will be directly
loaded into AC when AC load input is 1
• SC is cleared after the execution of the complete instruction
 Increment the data on memory location 50H and store
it on memory location 60H

• INC
– D7I’T3B5: AC ← AC+1, SC ← 0
– IR = 0,111,0000,0010,0000 (I’D7B5)
• Only AC is involved for data processing
• Increment of AC will be 1
• SC is cleared after the execution of the complete instruction
 Increment the data on memory location 50H and store
it on memory location 60H

• STA
– D3T4: M[60H] ← AC, SC ← 0
– IR = 0,011,0000,0110,0000 (I’D3,60H)
• AC is source, so it should be selected via main BUS control
meaning X4 should be 1
• Memory is destination so memory write should be 1
• SC is cleared after the execution of the complete instruction
 Increment the data on memory location 50H and store
it on memory location 60H

• Memory Read = D2T4 + R’T1

• X7 = D2T4 + R’T1
• DR (Load) = D2T4
• AC (Load) = D2T5
• AC (INC) = D7I’T3B5
• X4 = D3T4
• Memory Write = D3T4
• SC (CLR) = D2T5 + D7I’T3B5 + D3T4
• In addition, the fetch and decode cycle before every instruction requires
– AR (Load) = R’T0
– IR (Load) = R’T1
– PC (INC) = R’T1