EE382V Fall 2006

VLSI Physical Design Automation

Placement (1)
Prof. David Pan
[email protected]
Office: ACES 5.434

10/22/08 1
 Problem formulation
• Input:
– Blocks (standard cells and macros) B1, ... , Bn
– Shapes and Pin Positions for each block Bi
– Nets N1, ... , Nm
• Output:
– Coordinates (xi , yi ) for block Bi.
– No overlaps between blocks
– The total wire length is minimized
– The area of the resulting block is minimized or given a fixed
die
• Other consideration: timing, routability, clock, buffering
and interaction with physical synthesis
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Different Wire Length

3
Different Routability/Chip Area

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 Placement can Make a Difference
• MCNC Benchmark circuit e64 (contains 230 4-LUT).
Placed to a FPGA.
Random Initial Final After Detailed
Placement Placement Routing

5
 Importance of Placement
• Placement is a fundamental problem for physical design
• Glue of the physical synthesis
• Becomes very active again in recent years:
– Many new academic placers for WL min since 2000
– Many other publications to handle timing, routability, etc.
• Reasons:
– Serious interconnect issues (delay, routability, noise) in deep-
submicron design
• Placement determines interconnect to the first order
• Need placement information even in early design stages (e.g., logic
synthesis)
– Placement problem becomes significantly larger
– Cong et al. [ASPDAC-03, ISPD-03, ICCAD-03] point out that
existing placers are far from optimal, not scalable, and not stable

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 Design Types
• ASICs
– Lots of fixed I/Os, few macros, millions of standard cells
– Placement densities : 40-80% (IBM)
– Flat and hierarchical designs
• SoCs
– Many more macro blocks, cores
– Datapaths + control logic
– Can have very low placement densities : < 40%
• Micro-Processor (µP) Random Logic Macros(RLM)
– Hierarchical partitions are placement instances (5-30K)
– High placement densities : 80%-98% (low whitespace)
– Many fixed I/Os, relatively few standard cells

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 Requirements for Placers (1)
• Must handle 4-10M cells, 1000s macros
– 64 bits + near-linear asymptotic complexity
– Scalable/compact design database (OpenAccess)
• Accept fixed ports/pads/pins + fixed cells
• Place macros, esp. with var. aspect ratios
– Non-trivial heights and widths
(e.g., height=2rows)
• Honor targets and limits for net length
• Respect floorplan constraints
• Handle a wide range of placement densities
(from <25% to 100% occupied), ICCAD `02

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 Requirements for Placers (2)

• Add / delete filler cells and Nwell contacts

• Ignore clock connections
• ECO placement
– Fix overlaps after logic restructuring
– Place a small number of unplaced blocks
• Datapath planning services
– E.g., for cores
• Provide placement dialog services
to enable cooperation across tools
– E.g., between placement and synthesis

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Optimal Relative Order:

A B C

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 To spread ...

A B C

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.. or not to spread

A B C

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 Place to the left

A B C

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… or to the right

A B C

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 Optimal Relative Order:

A B C

Without “free” space the problem is dominated by order

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Placement Footprints:
Standard Cell:

Data Path:

IP - Floorplanning

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Placement Footprints:

Core

Reserved areas

IO Control

Mixed Data Path &

sea of gates:

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Placement Footprints:

Perimeter IO

Area IO

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Unconstrained
Placement

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Floor planned
Placement

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VLSI Global Placement Examples

bad placement good placement

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 Major Placement Techniques
• Simulated Annealing
– Timberwolf package [JSSC-85, DAC-86]
– Dragon [ICCAD-00]
• Partitioning-Based Placement
– Capo [DAC-00]
– Fengshui [DAC-2001]
• Analytical Placement
– Gordian [TCAD-91]
– Kraftwerk [DAC-98]
• FastPlace [ISPD-04]
• Hall’s Quadratic Placement
• Genetic Algorithm

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 Outline
• Wire length driven placement
• Main methods
– Simulated Annealing
• Gate-Array: Timberwolf package
• Standard-Cell: Timberwolf package, Dragon
– Partition-based methods
– Analytical methods
– Timing, congestion and other considerations
• Global placement (rough location)
• Detailed placement (legalization)

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 A down-to-the-earth method
• Clustering growth
– Select unplaced components and place them in slots
– SELECT: choose the unplaced component that is most
strongly connected to all (or any single) of the placed
component
– PLACE: place the selected component at a slot such
that a certain “cost” of the partial placement is
minimized
– Simple and fast: ideal for initial placement

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Simulated Annealing Based Placement
( I ) “ The Timberwolf Placement and Routing Package”, Sechen,
Sangiovanni; IEEE Journal of Solid-State Circuits, vol SC-20, No. 2(1985)
510-522
“Timber wolf 3.2: A New Standard Cell Placement and Global Routing
Package” Sechen, Sangiovanni, 23rd DAC, 1986, 432-439
Timber wolf
Stage 1
❁ Modules are moved between different rows as well as within the same
row
❁ modules overlaps are allowed
❁ when the temperature is reduced below a certain value, stage 2 begins

Stage 2
❁ Remove overlaps
❁ Annealing process continues, but only interchanges adjacent modules
within the same row

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 Solution Space

All possible arrangements of modules

into rows possibly with overlaps

overlaps

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 Neighboring Solutions
Three types of moves:
.
M1: Displace a module to .
a new location

M2: Interchange two

modules

M3: Change the orientation of a module

1 2 2 1 1 2
Axis of
reflections
3 4 3 4 3 4

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 Move Selection

 Timber wolf first try to select a move betwee M1 and M2

Prob(M1)=4/5 M1: Displacement
M2: Interchange
Prob(M2)=1/5
M3: Reflection

 If a move of type M1 is chosen ( for certain module) and

it is rejected, then a move of type M3 (for the same
module) will be chosen with probability 1/10
Restriction on:
 How far a module can be displaced
 What pairs of modules can be interchanged

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 Move Restriction
Range Limiter
❁ At the beginning, R is very large, big enough to
contain the whole chip
❁ Window size shrinks slowly as the temperature
decreases. In fact, height and width of R ∝ log(T)
❁ Stage 2 begins when window size are so small
that no inter-row modules interchanges are
possible

Rectangular window R

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 Cost Function
net i
Ψ = C1+C2+C3
hi
C1 : ∑(α i w i + β i h i ) wi
i
α i, β i are horizontal and vertical weights, respectively
α i =1, β i =1 ⇒1/2 •perimeter of bounding box
❁ Critical nets: Increase both α i and β i

❁ Preferred metal layer routing: if vertical wirings

are “cheaper” than horizontal wirings, we can use
smaller vertical weights, i.e. β i< α i

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 Cost Function (Cont’d)

C2: Penalty function for module overlaps

O(i,j) = amount of overlaps in the X-dimension
between modules i and j
C2 = ∑(O (i , j ) + α ) 2

i≠ j

α — offset parameter to ensure C2 → 0 when T →

0
C3: Penalty function that controls the row lengths
Desired row length = d( r )
l( r ) = sum of the widths of the modules in row r
C3 = ∑β l (r ) − d ( r )
r

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 Annealing Schedule

• Tk = r(k)•T k-1 k= 1, 2, 3, ….
r(k) increase from 0.8 to max value
0.94 and then decrease to 0.1
• At each temperature, a total number
of K•n attempts is made
n= number of modules
K= user specified constant

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 Dragon2000:
Standard-Cell Placement Tool for Large
Industry Circuits

M. Wang, X. Yang, and M. Sarrafzadeh,

ICCAD-2000
pages 260-263

10/22/08 33
 Main Idea
• Simulated annealing based
– 1.9x faster than iTools 1.4.0 (commerical version of TimberWolf)
– Comparable wirelength to iTools (i.e., very good)
– Performs better for larger circuits
– Still very slow compared with than other approaches
– Also shown to have good routability
• Top-down hierarchical approach
– hMetis to recursively quadrisect into 4h bins at level h
– Swapping of bins at each level by SA to minimize WL
– Terminates when each bin contains < 7 cells
– Then swap single cells locally to further minimize WL
• Detailed placement is done by greedy algorithm

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 Outline
• Wire length driven placement
• Main methods
– Simulated Annealing
• Gate-Array: Timberwolf package
• Standard-Cell: Timberwolf package, Grover, Dragon
– Partition-based methods
– Analytical methods

• Timing and congestion consideration

• Newer trends

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 Partition based methods
• Partitioning methods
– FM
– Multilevel techniques, e.g., hMetis
• Two academic open source placement tools
– Capo (UCLA/UCSD/Michigan): multilevel FM
– Feng-shui (SUNY Binghamton): use hMetis
• Pros and cons
– Fast
– Not stable

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 Partitioning-based Approach
• Try to group closely connected modules together.
• Repetitively divide a circuit into sub-circuits such that the
cut value is minimized.
• Also, the placement region is partitioned (by cutlines)
accordingly.
• Each sub-circuit is assigned to one partition of the
placement region.

Note: Also called min-cut placement approach.

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 An Example
Cutline

Circuit

Placement
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 Variations
• There are many variations in the partitioning-based
approach. They are different in:
– The objective function used.
– The partitioning algorithm used.
– The selection of cutlines.

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Partitioning:

Objective:

Given a set of interconnected blocks, produce two sets that

are of equal size, and such that the number of nets
connecting the two sets is minimized.

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FM Partitioning:

Initial Random Placement

list_of_sets = entire_chip;
while(any_set_has_2_or_more_objects(list_of_sets))
{
for_each_set_in(list_of_sets)
{
partition_it();
}
/* each time through this loop the number of */ After Cut 1
/* sets in the list doubles. */
}

After Cut 2
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FM Partitioning:
Moves are made based on object gain.

Object Gain: The amount of change in cut crossings

that will occur if an object is moved from
its current partition into the other partition

-1 0 2
- each object is assigned a
gain
- objects are put into a sorted 0
gain list 0 -
-2
- the object with the highest gain
from the larger of the two sides
is selected and moved.
- the moved object is "locked" 0 0
- gains of "touched" objects are -2
recomputed
-1
- gain lists are resorted
1
-1
1

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FM Partitioning:

-1 0 2

0
0 -
-2

0 0
-2
-1
1
-1
1

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 -1 -2 -2

0
-2 -
-2

0 0
-2
-1
1
-1
1

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 -1 -2 -2

0
-2 -
-2

0 0
-2
-1

1 1
-1

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 -1 -2 -2

0
-2 -
-2

0 0
-2
-1
1
1
-1

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 -1 -2 -2

0
-2 -
-2

0 -2
-2
1 -1
-1
-1

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 -1 -2 -2

-2 -
-2 0

0 -2
-2
1 -1
-1
-1

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 -1 -2 -2

-2 -
-2 0

0 -2
-2
1 -1
-1
-1

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 -1 -2 -2

-2 1
-2
0

-2 -2
-2
1 -1
-1
-1

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 -1 -2 -2

-2 1
-2
0

-2 -2
1 -2

-1
-1
-1

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 -1 -2 -2

-2 1
-2
0

-2 -2
1 -2

-1
-1
-1

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 -1 -2 -2

-2 1
-2
0

-2 -1
-2
-2

-3
-1
-1

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 -1 -2 -2

1
-2
-2
0

-2 -1
-2
-2

-3
-1
-1

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 -1 -2 -2

1
-2
-2
0

-2 -1
-2
-2

-3
-1
-1

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 -1 -2 -2

-1
-2
-2
-2

-2 -1
-2
-2

-3
-1
-1

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 Quadrature Placement Procedure

3a
1
3b

4a 2 4b

• Very suitable for circuits with high routing density in

the centre.

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 Bisection Placement Procedure
3a
2a
3b
1
3c
2b
3d

5a 4 5b
6a 6b 6c 6d

• Good for standard-cell placement.

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Terminal Propagation Algorithm by Dunlop
and Kernighan

“A Procedure for Placement of

Standard-Cell VLSI Circuits”,
TCAD, 4(1):92-98, Jan. 1985.

10/22/08 59
Problem of Partitioning Subcircuits

A B

A B B
A

Cost of these 2 partitionings are not the same.

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 Terminal Propagation
• Need to consider nets connecting to external terminals or
other modules as well.
• Do partitioning in a breath-first manner (i.e., finish all
higher-level partitioning first).
The Dummy Terminal will try
to pull B to the top partition.
Dummy Terminal

A A B
A B B

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Terminal Propagation

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 Creating Circuit Rows
• Terminal propagation reduce overall area by ~30%
• Creating rows
– Choose α and β preferably to balance row to balance row
length (during re-arrangement )

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Can Recursive Bisection Alone Produce Routable
Placement?
(Name of placer: Capo)

Andrew Caldwell, Andrew Kahng, and Igor

Markov
DAC-2000

10/22/08 64
 Capo Overview

• Standard cell placement, Fixed-die context

• Pure recursive bisectioning placer
– Several minor techniques to produce good bisections
• Produce good results mainly because:
– Improvement in mincut bisection using multi-level idea in the
past few years
– Pay attention to details in implementation
• Implementation with good interface (LEF/DEF and
GSRC bookshelf) available on web

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 Capo Approach

• Recursive bisection framework:

– Multi-level FM for instances with >200 cells
– Flat FM for instances with 35-200 cells
– Branch-and-bound for instances with <35 cells
• Careful handling partitioning tolerance:
– Uncorking: Prevent large cells from blocking smaller cells to
move
– Repartitioning: Several FM calls with decreasing tolerance
– Block splitting heuristics: Higher tolerance for vertical cut
– Hierarchical tolerance computation: Instance with more
whitespace can have a bigger partitioning tolerance

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 Partitioning:

Pros:
- very fast
- great quality
- scales nearly linearly with problem size

Cons:
- non-trivial to implement
- very directed algorithm, but this limits the ability to deal with
miscellaneous constraints
- Not stable (if there is minor change)

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 Summary for Partition Based Placement

• Improvement in mincut partitioning are conducive to

better wirelength and congestion
• Routable placements can be produced in most cases
without explicit congestion management
– Explicit congestion control may still be useful in some cases
• Better weighted wirelength often implies better routed
wirelength, but not always

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