UNIT – II

GATELEVEL
MINIMIZATIO
N

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 1

 The Map
 The Method
complexity of the digital logic gates that
implement a Boolean function is directly related to
the complexity of the algebraic expression from
which the function is implemented.
 Although, the truth table representation of a
function is unique, when expressed algebraically ,
it can appear in many different forms.
 The procedure of minimization of expressions by

substituting equivalent rules of Boolean algebra is

awkward because it lacks specific rules to predict
each succeeding step in the manipulative process.
 The map method provides a simple straight
forward procedure for minimizing Boolean
functions. This method may be regarded as a
pictorial form of a truth table.
 The Map method is also known as the Karnaugh

map or LOGIC DESIGN/IT II-I Sem/GRIET

UNIT-II/DIGITAL P Bharathi 2
 The Map Method -

continued.,
The map is a diagram made up of squares, with
each square representing one minterm of the
function. Since any Boolean function can be
expressed as a sum of minterms, it follows that a
Boolean function is recognized graphically in the
map from the area enclosed by those squares
whose minterms are included in the function.
 The map presents a visual diagram of all possible
ways a function may be expressed in standard
form.
 By recognizing various patterns, the user can
derive alternative algebraic expressions for the
same function, from which the simplest can be
selected.
 The simplified expressions produced by the map
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 3
 Two Variable
 The two Map
variable map isused to
represent a function with two
variables.
 There are four minterms for two
variables: hence the map consists of
four squares, one for each minterm.

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 Representation of Functions in
the Map

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Rules for simplification of K-
map
1.Groups may not contain zero.
2.We can group 1,2,4,8 or 2^n cells.
3.Each group should be as large as possible.
4.Cells containing 1 must be grouped.
5.Groups may overlap.
6.Opposite grouping and corner grouping is
allowed.
7.There should be as few groups as possible.

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 Three Variable
Map
 The three variable map is used to
represent a function with three
variables.
 There are eight minterms for three
binary variables. Therefore the map
consists of eight squares.
 Here the minterms are not arranged
in a binary sequence, but in a
sequence similar to a Gray code. The
characteristic of this sequence is that
only bit changes in value from one
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 Three Variable
Map

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 Minimization

Procedure
The combination of adjacent squares that is
useful during the simplification process is
easily determined from inspection of the
three variable map:
 One square represents one minterm, giving a
term of three literals.
 Two adjacent squares represent a term of
two literals.
 Four adjacent squares represent a term of
one literal.
 Eight adjacent squares represent the
function equal to 1.
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 Example

1
Simplify the Boolean function
F(x,y,z)=Σ(2,3,4,5)
 First, a 1 is marked in each minterm
that represents the function.
 The next step is to find possible
adjacent squares.

F(x,y,z)=
Σ(2,3,4,5)=x
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIETy+xy P Bharathi
1 1
10
 Example

2
Simplify the Boolean function
F(x,y,z)=Σ(3,4,6,7)

F(x,y,z)=
Σ(3,4,6,7)=yz+xz1

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 Example

3
Simplify the Boolean function
F(x,y,z)=Σ(0,2,4,5,6)

F(x,y,z)=Σ(0,2,4,5,6)=z1+xy1

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 Example
 Given
4
the Boolea functio
F=A1C+A1B+AB1C+ n n
BC

 And find itthe
Express in minimal
terms of sum of products expression
 Three product terms in the expression have two
minterms
literals and are represented in a three variable
map by two squares each.

The two squares corresponding to the term A1C
are :001,011

The two squares corresponding to the term A1B
are :010,011

The square corresponding to the term AB1C are :101

The two squares corresponding to the term BC
are :011,111
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F(A,B,C)=A1C+A1B+AB1C+BC

1. A’C=A’C(B+B’)=A’BC+A’B’C
2. A’B=A’B(C+C’)=A’BC+A’BC’
3. BC=BC(A+A’)=ABC+A’BC
F(A,B,C)=
=A’BC+A’B’C+A’BC+A’BC’+AB’C+ABC
+A’BC
=011+001+011+010+101+111+011
=011+001+010+101+111
=m3+m1+m2+m5+m7=Σ(1,2,3,5,7)
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 F=A1C+A1B+AB1C+BC=C+A1B

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 Four Variable
 The four Mapmap is used to
variable represent a
function with four variables.
 There are sixteen minterms for four binary
variables. Therefore the map consists of sixteen
squares.
 The rows and columns are numbered in a
Graycode sequence, with only one digit changing
value between two adjacent rows and columns.
 The map minimization of four variables Boolean
functions is similar to the method used to
minimize three variable functions. Adjacent
squares are defined to be squares next to each
other. In addition, the map is considered to lie on
a surface with the top and bottom edges, as well
as the right and left edges, touching each other to
form adjacent squares.
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 Four Variable
Map

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 Minimization

Procedure
The combination of adjacent squares that is
useful during the simplification process is
easily determined from inspection of the
four variable map:
 One square represents one minterm, giving a
term of four literals.
 Two adjacent squares represent a
termof three literals.
 Four adjacentsquares representa term of
two literals.
 Eight adjacentsquaresrepresent a
term of one literal.
 Sixteen adjacentsquares represent the
function equal to 1.
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 Example
5
 Simplify the functio
Boolean
F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13 n

,14)

F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14)=y1+w1z1
+xz 1
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 Example
 Simplify
6
the Boolean
function F=A1B1C1+B1CD1+A1BCD1+AB1C1
 The function has four variables and consists
of three terms with each three literals, and
one term of four literals.
 Each term of three literals is represented in
the map by two squares.

The two squares corresponding to the term A1B1C1
are :0001,0000

The two squares corresponding to the term B1CD1
are :0010,1010

The two square corresponding to the term AB1C1
are :1000,1001
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 F=A1B1C1+B1CD1+A1BCD1+AB1C1=B1D1+B1C1+
A1CD1

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 Prime
 Implicants
A prime implicant is a product term obtained by
combining the maximum number of possible
adjacent squares in the map.
 If a minterm in a square is covered by only on
prime implicant, that prime implicant is called
Essential prime implicant.

 Pair: pair is a group of two logical 1’s in a Karnaugh

map. A pair eliminates one variable in the output
expression.
 Quad: Quad is a group of four logical 1’s in a
Karnaugh map. A quad eliminates two variable in
the output expression.
 Octet: Octet is a group of eight logical 1’s in a
Karnaugh map. An octet eliminates three variable
in the output expression.
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 Five Variable
Map
 Maps for more than four variables are
not as simple to use. A five variable
map needs
32 squares and a six variable map
needs 64 squares. When the number
of variables becomes large, the
number of squares becomes
excessively large and the geometry
of combining adjacent squares
becomes more complicated.
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 Five Variable
Map
 The five variable map can be shown
as two four variable maps.

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 It consists of two four variable maps with variables
A,B,C,D and E. Variable A distinguishes between
the two maps as indicated on the top of the
diagram.
 Minterms 0 to 15 belong with A=0 and minterms

16 to 31 belong with A=1.

 Each four variable map retains its adjacency when

taken
separately.
 In addition each square in the A=0 map is adjacent

to the corresponding square in A=1 map. For

example, minterm 4 is adjacent to minterm 20
and minterm 15 to 31.
 The best way to visualize this new rule for adjacent

squares is to consider the two half maps as being

one on top
UNIT-II/DIGITAL LOGICof the other.
DESIGN/IT Any two Psquares
II-I Sem/GRIET Bharathi that fall 25
 Example
7
Simplify the Boolean function
F(A,B,C,D,E)=Σ(0,2,4,6,9,13,21,23,25,2
9,31)

F=A1B1E1+BD1E+ACE
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 Product of Sums
 Simplification
The procedure for obtaining a minimized
function in product of sums follows from
the basic properties of Boolean functions.
The 1’s placed in the squares of the map
represent the minterms of the function.
 The minterms not included in the function

denote the complement of the function.

 So, if we mark the empty squares by 0’s

and combine them into valid adjacent

squares we obtain a simplified expression
for F1. the complement of F1 gives us back
the function F. because of the generalized
DeMorgan’s theorem, the function so
obtained is automatically in the product of
sums form.
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 27
 Example
8
 Simplify the following Boolean
function in Product of
Sums form:
F(A,B,C,D)=∑(0,1,2,5,8,9,10)

UNIT-II/DIGITAL LOGIC
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2
 If thesquares marke wit 0’s are
d h
combined,
complemented obtain the simplifie
function:
we
F 1=AB+CD+BD1 d
 (F1)1=(AB+CD+BD1)1
=(A1+B1)(C1+D1)(B1+D)

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 29

 Two Level
 The
Implementation
implementation of the simplified
expression in sum of products form can be
done as follows: with a group of AND
gates, one for each AND term. The outputs
of the AND Gates are connected to the
inputs of a single OR Gate.
 For example, F=B1D1+B1C1+A1C1D

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 The implementation of the simplified
expression in products of Sums form can
be done as follows: with a group of OR
gates, one for each OR term. The outputs
of the OR Gates are connected to the
inputs of a single AND Gate.
 For Example, F=(A1+B1)(C1+D1)(B1+D)

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 Don’t Care

Conditions
Functions that have unspecified outputs for
some input combinations are called
incompletely specified functions.
 In most applications, we simply don’t care
what value is assumed by the function for
the unspecified minterms. So it is
customary to call the unspecified minterms
of a function don’t care conditions.
 These don’t care conditions can be used on
a map to provide further simplification of
the Boolean expression.

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 32

 A don’t care minterm is a combination
of variable whose logical value is not
specified.
 To distinguish the don’t care condition
from 1’s and 0’s, an X used.
 Thus an X inside a square in the map
indicates that we don’t care whether
the value of 0 or 1 is assigned to
function for the particular minterm.
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 33
 Example
9
 Simplify the Boolean functio
F(w,x,y,z)=Σ(1,3,7,11,15) n has
whichcare conditons d(w,x,y,z)=
don’t
 Σ(0,2,5) the

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 Either one of the precedingtwo
expressions satisfies the conditions stated
for the example
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 NAND & NOR
Implementation
 Digital circuits are frequently
constructed with NAND or NOR gates
rather than with AND and OR gates.
 NAND and NOR gates are easy to
fabricate with electronic components
and are the basic gates used in all IC
digital logic families.

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 36

 NAND
Circuits
 The NAND gate is said to be universal
gate because any digital system can
be implemented with it.
 To show that any Boolean function can
be implemented with NAND gates,
we need only show that the logical
operations of AND, OR and
complement can be obtained with
NAND gates only.

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 NAND
Implementation

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 Graphic symbols for NAND
Gates

AND-
INVERT

INVERT-
OR

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 Two Level
 The
Implementation
implementation of Boolean
functions with NAND gates requires
that the function be in sum of
products form.
 For example, F=AB+CD

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 40

 The procedure for obtaining the logic
diagram of Boolean function is as follows:

Simplify the function and express it in sum of
products.

Draw a NAND gate for each product term of the
expression that has atleast two literals. This
constitutes the first level gates.

Draw single gate using the AND Invert or Invert
OR graphic symbol in the second level, with
inputs coming from outputs of first level gates.

A term with single literal requires an inverter in
the first level. However, if the single literal is
complemented, it can be connected directly to
an input of the second level NAND Gate.
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 41
 Example
10
 Implement the following Boolean
function with NAND Gates:
F(x,y,z)=(1,2,3,4,5,7)
 The first step is to simplify the
function in sum of products. This is
done by means of the map method.

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 42

 =xy1+x1y
+z

=xy1+x1y
+z

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 MultilevelNAND
 The
Circuits
general procedure for converting
a
multilevel AND-OR diagram into an all
NAND diagram using mixed notation is as
follows:

Convert all AND gates to NAND gates with AND-
invert graphic symbol.

Convert all OR gates to NAND gates with invert-
OR graphic symbols.

Check all the bubbles in the diagram. For every
bubble that is compensated by another small
circle along the same line, insert an inverter or
complement the input literal.
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 44
 Example
 Implement 11
the following function
in multilevel NAND form
F=A(CD+B)+BC1

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 Example
12consider the multilevel
As another example,
Boolean function F=(AB1+A1B)(C+D1)

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 NOR
Implementation
 The NOR Gate is another universal
logic gate that can be used to
implement any Boolean functions.

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 Two Graphic Symbols ofNOR
Gate

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 48

 Two level NOR
 A
implementation
two level implementation with NOR gates
requires that the function be simplified in product
of sums.
 Remember that the simplified product of sums

expression is obtained from the map by combining

the 0’s and complementing.
 A product of sums expression is implemented with

a first level of OR gates that produce the sum

terms followed by a second level AND gate to
produce the product.
 The transformation from the OR-AND diagram to a

NOR diagram is achieved by changing the OR

gates to NOR gates with OR- invert graphic
symbols and the AND gate with an invert-AND
graphic symbol.
 A single literal term going into the second level

gate must
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 49
 Example
13
 Show the two level implementation of
the Boolean Function using NOR
gates F=(A+B)(C+D)E

UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 50

 Exclusive – OR
 The
Function
exclusive – OR function
denoted
(XOR), by the symbol + , is a
operation
logical that performs the following
Boolean operation: x + y=xy1+x1y
 It is equal to 1 if only x is equal to 1 or
if only y is equal to 1, but not when
both are equal to 1.
 The exclusive NOR also known as
equivalence, performs the following
boolean Operation: (x + y)1=xy+x1y1
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 Logic Diagrams for
XOR

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 Parity Generation &

Checking
A parity bit is used for detecting errors
during transmissions of binary information.
 A parity bit is an extra bit included with a
binary message to make the number of 1’s
either even or odd.
 The message, including the parity bit is
transmitted and then checked at the
receiving end for errors.
 An error is detected if the checked parity
does not correspond with the one
transmitted.
 The circuit that generates the parity bit in
the transmitter is called a parity generator.
The circuit that checks the parity in the
receiver is called parity checker.
UNIT-II/DIGITAL LOGIC DESIGN/IT II-I Sem/GRIET P Bharathi 53
 Parity Bit

Generation
As an example, consider a 3-bit message to be
transmitted together with an even parity bit. For
even parity the parity bit P is to be generated to
make the number of 1’s in the message even
including the parity.
Three – Bit Parity Bit
Message
X Y Z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
P Bharathi
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 Parity Bit
Checking
FOUR BITS PARITY CHECK
RECIEVED
X Y Z P C
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
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 Four Bit Even Parity Checker

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