Academic Session 2025-26
ODD Semester Jul-Dec 2025
UNIVERSITY INSTITUTE OF ENGINEERING
DEPARTMENT OF COMPUTER SCIENCE &
ENGINEERING
BACHELOR OF ENGINEERING
CSE/IT/ THIRD SEMESTER
COMPUTER ORGANIZATION & ARCHITECTURE
(24CST-201/24ITT-201)
Unit No. 1 Chapter No. 1.2 Lecture No. 1.2.3
Topic : Multiplication Algorithms
Er. Shikha Atwal (E11186) Assistant Professor
Learning Objectives
1
• To understand how multiplication is performed using
fixed-point number representation in digital systems.
• To learn standard fixed-point multiplication algorithms
like array multiplier and Booth’s algorithm.
• To analyze the trade-offs in terms of accuracy, speed,
and hardware complexity in implementing fixed-point
multiplication.
Content
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1. Multiplication of unsigned numbers
1.1. Array Multiplier
1.2. Sequential Circuit Multiplier
2. Multiplication of signed numbers
2.1. The Booth’s Algorithm
Multiplication of Unsigned numbers
3
• Product of 2 n-bit numbers is at-most 2n bit number.
• Multiplication of two integer numbers 13 and 11 is
below.
Array Multiplier
4
• Binary multiplication can be implemented in a
combinational two-dimensional logic array called array
multiplier.
• The main component in each in each cell is a full adder,
FA.
• The AND gate in each cell determines whether a
multiplicand bit mj, is added to the incoming partial
product bit based on the value of the multiplier bit, qi.
Array Multiplier
5
• Each row i, where 0<=i<=3, adds
the multiplicand (appropriately
shifted) to the incoming parcel
product, PPi, to generate the
outgoing partial product, PP(i+1),
if qi =1.
• If qi =0, PPi is passed vertically
downward unchanged. PP0 is all
0’s and PP4 is the desired
product. The multiplication is
shifted left one position per row
Sequential Circuit Multiplier
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• Multiplication is performed as a series of (n) conditional addition and
shift operation.
• The multiplier and multiplicand are loaded into two registers Q and M.
Third register A and C are cleared to 0.
• In each cycle it performs 2 steps:
(a) If LSB of the multiplier qi =1, control sequencer generates Add signal
which adds the multiplicand M with the register A and the result is
stored in A.
(b) If qi =0, it generates Noadd signal to restore the previous value in
register A.
• Right shift the registers C, A and Q by 1 bit.
Sequential Circuit Multiplier
7
Multiplication of Signed numbers
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• It is the multiplication of 2’s-
complement operands, generating a
double-length product.
• In the case of a positive multiplier
and a negative multiplicand, When
we add a negative multiplicand to a
partial product, we must extend the
sign-bit value of the multiplicand to
the left as far as the product will
extend.
Booth’s Algorithm
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1. Multiplicand is placed in BR and Multiplier in
QR
2. Accumulator register AC, Qn+1 are initialized to
0
3. Sequence counter SC is initialized to n (number
of bits)
4. Compare Qn and Qn+1 and perform the
following:
01 –> AC=AC+BR
10 –> AC=AC+BR’+1
00 –> No arithmetic operation
11 –> No arithmetic operation
Booth’s Algorithm
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5. ASHR- Arithmetic Shift right
AC, QR
6. Decrement SC by 1
7. The final product will be store
in AC and QR Registers.
Applications
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• Digital Signal Processing (DSP): Used in audio, video, and image processing
systems for filtering, convolution, and FFT operations. Array and Booth's
multipliers offer fast computation, crucial for real-time signal processing.
• Embedded Systems and Microcontrollers: Sequential multipliers are preferred
in low-power, cost-sensitive applications like sensors, wearables, and IoT
devices where speed is less critical.
• Graphics and Game Engines: Array and Booth’s multipliers are used for
geometric transformations, 3D rendering, and animation due to their high-
speed capabilities.
• Control Systems in Robotics and Automation: Perform fixed-point
multiplication for feedback calculations, motor control, and sensor data
interpretation with efficient multiplier units.
Summary of the Lecture
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1. Fixed-point multiplication algorithms are essential for performing
efficient arithmetic in digital systems where floating-point units are
impractical.
2. Techniques like the Array Multiplier provide high-speed, parallel
processing suitable for performance-critical applications such as DSP and
graphics.
3. Sequential Multipliers, on the other hand, are hardware-efficient,
making them ideal for embedded and low-power systems.
4. Booth’s Algorithm improves multiplication of signed numbers by
reducing the number of partial products, offering a balance between
speed and complexity.
5. Together, these algorithms support a wide range of applications from IoT
to real-time processing and automation.
Next Lecture
13
• Levels of Programming Language
• Assembly Language
• Instruction Cycle
• Addressing modes
• Operations
• Types of Instruction
• Instruction format
Quiz
14
Q1. What is the main advantage of Booth’s multiplication algorithm over standard fixed-point multiplication?
A. It requires more hardware resources
B. It simplifies unsigned multiplication
C. It reduces the number of partial products for signed numbers
D. It eliminates the need for adders
Q2. Which of the following correctly describes an Array Multiplier?
A. Performs multiplication using a single adder and multiple cycles
B. Uses sequential logic to perform addition
C. Multiplies all bits in parallel using combinational logic
D. Requires control signals for timing and sequencing
Q3. In a sequential multiplier, what is the primary reason it takes longer to complete multiplication than an array
multiplier?
A. Uses more hardware components
B. Processes one partial product per clock cycle
C. Doesn’t support signed numbers
D. Requires floating-point support
References/ Articles/ Videos
15
Text Books:
● Carl Hamacher, Zvonko Vranesic, Safwat Zaky, and Naraig Manjikian, ‘Computer
Organization and Embedded Systems’, Sixth Edition, McGraw-Hill Education, 2012.
● M. Morris Mano, ‘Computer System Architecture’, Third Edition, Pearson Education, 2023.
Reference Books:
● John P. Hayes, ‘Computer Architecture and Organization’, Third Edition, McGraw-Hill
Education, 1998.
● William Stallings, ‘Computer Organization and Architecture: Designing for Performance’,
Eleventh Edition, Pearson Education, 2021.
● Vincent P. Heuring, and Harry F. Jordan, ‘Computer Systems Design and Architecture’,
Second Edition, Pearson Education, 2003.
References/ Articles/ Videos
16
Reference Website
https://en.wikipedia.org/wiki/Multiplication_algorithm
https://ijariie.com/AdminUploadPdf/STUDY_OF_MULTIPLICATION_ALGORITHMS_IN_COMPUTERS_ijar
iie8777.pdf?srsltid=AfmBOopTIsa4H9TblS_4UsjhnNxfJLP7FY48hqW3ww1_edPRCOuqCkoJ
https://www.geeksforgeeks.org/multiplication-algorithm-in-signed-magnitude-representation/
Video References
https://youtu.be/bySS-b--W6g?si=2RFRsOQJNibTAHIh
https://youtu.be/2IxktI0BOu4?si=Oi_clj6JaqaueHhG
https://youtu.be/U62iP8RkZIk?si=kKQYo_Fu6wfvxvfB
Faculty-curated videos, NPTEL,
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Coursera, LinkedIn, or other relevant
learning resources
• NPTEL: https://www.youtube.com/watch?v=ZidI6BVYrQE
• NPTEL: https://www.youtube.com/watch?v=5-PI4T25OXI
• https://www.linkedin.com/learning/c-programming-for-e
mbedded-applications-14537235/fixed-point-math
• https://www.geeksforgeeks.org/computer-organization-b
ooths-algorithm/
• https://vlabs.iitkgp.ac.in/coa/exp7/index.html
Class-Wise Feedback
18
Faculty members are encouraged to generate a class specific QR
code at the end of each session to collect brief student feedback.
This can support self-reflection, improve teaching practices, and
allow students to share insights, suggestions, or concerns
anonymously.
19
Thank You
