Memory Management

Memory Management

• Background
• Swapping
• Contiguous Memory Allocation
• Paging
• Structure of the Page Table
• Segmentation
• Example: The Intel Pentium
 Background
• Program must be brought (from disk) into memory and placed within a process for it
to be run
• Main memory and registers are only storage CPU can access directly
• Register access in one CPU clock (or less)
• Main memory can take many cycles
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct operation
A pair of base and limit registers define the logical address space.

The Base register holds the smallest legal physical memory address
The limit register specifies the size of the range.
For example,
if the base register holds 300040 and
the limit register is 120900, then the program can legally access
all addresses from 300040 through 420939 (inclusive).
Base and Limit Registe
 Binding of Instructions and Data to Memory

Address binding of instructions and data to memory addresses can happen at three different
stages
Compile time: If memory location known
a priori, absolute code can be generated;
must recompile code if starting location
changes
Load time: Must generate relocatable
code if memory location is not known at
compile time
Execution time: Binding delayed until run
time if the process can be moved during its
execution from one memory segment to
another. Need hardware support for
address maps (e.g., base and limit registers)
 Logical vs. Physical Address Space
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit

Logical and physical addresses are the same in compile-time and load-time
address-binding schemes.

logical (virtual) and physical addresses differ in execution-time address-binding

scheme.
 Memory-Management Unit (MMU)
Hardware device that maps virtual to physical address
In MMU scheme, the value in the relocation register is added to every
address generated by a user process at the time it is sent to memory.
The user program deals with logical addresses; it never sees the real
physical addresses.
Dynamic Relocation Using a Relocation Register

The above figure shows that dynamic re-location which implies

mapping from virtual addresses space to physical address space
and is performed by the hardware at run time.
•Re- location is performed by the hardware and is invisible to
the user dynamic relocation makes it possible to move a partially
executed process from one area of memory to another without
affecting
 Dynamic Linking

• Dynamic linking is the process of linking libraries to a program at runtime rather

than at compile time

• Instead of embedding the library code into the executable, the program contains
references to the shared library.

• When the program is executed, the operating system loads the required shared
libraries into memory and links them dynamically.

• Small piece of code, stub, used to locate the appropriate memory-resident library
routine

• Dynamic linking is particularly useful for libraries

• System also known as shared libraries

Swapping
• A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution

• Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these
memory images

• Roll out, Roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed

• Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped

• Modified versions of swapping are found on many systems (i.e., UNIX,

Linux, and Windows)

• System maintains a ready queue of ready-to-run processes which have

memory images on disk
Schematic View of Swapping
Contiguous Allocation
• Main memory usually into two partitions:
• Resident operating system, usually held in low memory with interrupt vector
• User processes then held in high memory

• Relocation registers used to protect user processes from each other, and from changing
operating-system code and data
• Base register contains value of smallest physical address
• Limit register contains range of logical addresses – each logical address must be less
than the limit register
• MMU maps logical address dynamically
Hardware Support for Relocation and Limit Registers
 Contiguous Allocation (Cont.)
• Main memory is divided into two partitions: one for the operating system and one for
user processes. User processes are allocated contiguous blocks of memory.
• Memory Allocation Strategies:
• Memory allocation is a crucial aspect of operating systems, and there are several
strategies to allocate memory to processes. Three common strategies are First Fit,
Best Fit, and Worst Fit.
• First Fit Allocation Allocates the first hole (available memory block) that is large
enough
Example:
Consider the following memory blocks and processes:
Memory Blocks: [20K, 100K, 40K, 200K, 10K]
Processes: P1 (90K), P2 (50K), P3 (30K), P4 (40K)
Allocation:
P1 is allocated to the second block (100K).P2 is allocated to the fourth block (200K).
P3 is allocated to the third block (40K).P4 cannot be allocated as no suitable block is
available.
Best Fit Allocates the smallest hole that is large enough, leaving the smallest leftover
hole
Example:
Consider the same memory blocks and processes as above.
Allocation:
P1 is allocated to the second block (100K).P2 is allocated to the third block (40K).
P3 is allocated to the fifth block (10K).P4 is allocated to the first block (20K).

Worst Fit Allocates the largest hole, leaving the largest leftover hole
Example:
Consider the same memory blocks and processes as above.
Allocation:
P1 is allocated to the fourth block (200K). P2 is allocated to the first block (20K).
P3 is allocated to the second block (100K).P4 cannot be allocated as no suitable block
is available.
 Fragmentation
• Fragmentation in operating systems refers to the inefficient utilization of memory
caused by dividing available memory into small, non-contiguous blocks. This occurs
when processes are loaded and removed from memory, leaving behind gaps that
cannot be effectively reused.
• Fragmentation impacts system performance by reducing memory efficiency and
slowing down operations.
• External Fragmentation – total memory space exists to satisfy a request, but it is not
contiguous
• Internal Fragmentation – allocated memory may be slightly larger than requested
memory; this size difference is memory internal to a partition, but not being used
• Data Fragmentation happens when data is stored in non-contiguous blocks, often
seen in file systems. This can lead to slower access times as the system must retrieve
data from multiple locations.
• Causes and Effects
Fragmentation is caused by dynamic memory allocation, where processes are loaded
and removed frequently. Over time, this creates small, unusable memory blocks. The
effects include slower system performance, wasted disk space, increased risk of
crashes, and reduced battery life in mobile devices due to higher disk activity.
 Paging
Definition: Paging divides both the main memory (RAM) and a
process's logical memory into fixed-size blocks. These blocks are:
• Pages: Logical memory blocks.
• Frames: Physical memory blocks
• The OS maps pages to frames, enabling processes to execute even if
their memory is scattered across different locations.
How Paging Works
• Logical Address: A process generates a logical address, which is
divided into:
• Page Number: Identifies the page in logical memory.
• Page Offset: Specifies the exact location within the page
Mapping: The OS uses a page table to map the page number to a
corresponding frame in physical memory.
Physical Address: The frame number and offset combine to form the
physical address.
Advantages
Efficient Memory Utilization: Eliminates external fragmentation.
Flexibility: Processes can use non-contiguous memory.
Swapping: Pages can be swapped between main memory and
secondary storage.
Disadvantages
Internal Fragmentation: Unused space within frames.
Overhead: Managing page tables requires additional memory and
processing.
Paging is widely used in modern operating systems to optimize
memory usage and improve multitasking capabilities.
Address Translation Scheme
• Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which contains base address of each
page in physical memory
• Page offset (d) – combined with base address to define the physical memory address that is
sent to the memory unit
page number page offset
p d
m-n n
• For given logical address space 2 and page size 2
m n

Page address is called logical address and represented by page number and the offset. Logical
Address = Page number +page offset
Frame address is called physical address and represented by a frame number and the offset.
Physical Address=Frame number +page offset
A data structure called page map table is used to keep track of the relation between a page of
a process to a frame in physical memory.
Paging Hardware
Paging Model of Logical and
Physical Memory
Paging Example

32-byte memory and 4-byte pages

Free Frames

Before allocation After allocation

 Implementation of Page Table

• Page table is kept in main memory

• Page-table base register (PTBR) points to the page table

• Page-table length register (PRLR) indicates size of the page table

• In this scheme every data/instruction access requires two memory accesses. One
for the page table and one for the data/instruction.

• The two memory access problem can be solved by the use of a special fast-lookup
hardware cache called associative memory or translation look-aside buffers
(TLBs)

• Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely
identifies each process to provide address-space protection for that process
Associative Memory

• Associative memory – parallel search

Page # Frame #

• Address translation (p, d)

• If p is in associative register, get frame # out
• Otherwise get frame # from page table in memory
Paging Hardware With TLB
 Effective Access Time

• Associative Lookup =  time unit

• Assume memory cycle time is 1 microsecond

• Hit ratio – percentage of times that a page number is

found in the associative registers; ratio related to
number of associative registers

• Hit ratio = 

• Effective Access Time (EAT)

EAT = (1 + )  + (2 + )(1 – )
=2+–
Memory Protection

• Memory protection implemented by associating

protection bit with each frame
• Valid-invalid bit attached to each entry in the page
table:
• “valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
• “invalid” indicates that the page is not in the process’
logical address space
Valid (v) or Invalid (i) Bit In A Page
Table
Shared Pages

• Shared code
• One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
• Shared code must appear in same location in the logical
address space of all processes.

• Private code and data

• Each process keeps a separate copy of the code and data.
• The pages for the private code and data can appear
anywhere in the logical address space.
Shared Pages Example
 Structure of the Page Table

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

Hierarchical Page Tables

• Break up the logical address space into multiple

page tables

• A simple technique is a two-level page table

Two-Level Page-Table Scheme
Two-Level Paging Example

• A logical address (on 32-bit machine with 1K page size) is

divided into:
• a page number consisting of 22 bits
• a page offset consisting of 10 bits
• Since the page table is paged, the page number is further
divided into:
• a 12-bit page number
• a 10-bit page offset
• Thus, a logical address is as follows:

page number page offset

pi p2 d
12 10 10
where pi is an index into the outer page table, and p2 is the
displacement within the page of the outer page table
Address-Translation Scheme
Three-level Paging Scheme
 Hashed Page Tables

• Common in address spaces > 32 bits

• The virtual page number is hashed into a page table.

• This page table contains a chain of elements hashing to the
same location.

• Virtual page numbers are compared in this chain

searching for a match.
• If a match is found, the corresponding physical frame is
extracted.
Hashed Page Table
Inverted Page Table

• One entry for each real page of memory.

• Entry consists of the virtual address of the page

stored in that real memory location, with
information about the process that owns that page.

• Decreases memory needed to store each page

table, but increases time needed to search the
table when a page reference occurs.

• Use hash table to limit the search to one — or at

most a few — page-table entries.
Inverted Page Table Architecture
 Segmentation
• Segmentation in an operating system is a memory management technique that divides the

logical address space of a process into variable-sized segments. Each segment represents a

logical unit of the program, such as code, data, or stack, and is assigned a name and length.

• Key Features of Segmentation:

• Logical Division: Memory is divided into segments based on the program's structure, such as

functions, arrays, or objects.

• Segment Table: Each process has a segment table that stores the base address and length of

each segment.

• Logical Address: A logical address consists of two parts:

• Segment Number: Identifies the segment.

• Offset: Specifies the location within the segment.

Advantages:
User-Friendly: Reflects the logical structure of programs, making it easier for programmers.
Efficient Memory Utilization: Segments can grow or shrink independently, reducing

fragmentation.
Protection: Each segment can have its own access rights, enhancing security.
Disadvantages:
Complexity: Managing segment tables and handling segmentation faults can be challenging.
External Fragmentation: Variable-sized segments can lead to gaps in memory.

Segmentation is widely used in modern operating systems to improve memory

management and align with the way users perceive and organize their programs.
User’s View of a Program
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

 Segmentation Architecture

• Logical address consists of a two tuple:

<segment-number, offset>,

• Segment table – maps two-dimensional physical

addresses; each table entry has:
• base – contains the starting physical address where the
segments reside in memory
• limit – specifies the length of the segment

• Segment-table base register (STBR) points to the

segment table’s location in memory

• Segment-table length register (STLR) indicates

number of segments used by a program;
segment number s is legal if s < STLR
 Segmentation Architecture (Cont.)

• Protection
• With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges

• Protection bits associated with segments; code

sharing occurs at segment level.

• Since segments vary in length, memory allocation is

a dynamic storage-allocation problem.

• A segmentation example is shown in the following

diagram.
Segmentation Hardware
Example of Segmentation