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Pull requests: gem5/gem5

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Pull requests list

arch-arm: Fix compile errors
#2691 opened Oct 22, 2025 by powerjg Loading…
1
stdlib: Remove GPU ip_discovery.bin if exists gpu gem5's GPU Simulation infrastructure
#2690 opened Oct 22, 2025 by abmerop Loading…
sim,mem-ruby: Define a CHI-TLM port mem-ruby Ruby caches, structures, and protocols sim General gem5 Simulation Components tests gem5's Testing Infrastructure
#2689 opened Oct 22, 2025 by giactra Loading…
base: Fix use-after-free warning base Regards gem5's base code. Found in "src/base"
#2686 opened Oct 22, 2025 by rogerchang23424 Loading…
mem-cache: register TagExtractor for SectorTag mem General Memory Systems (e.g., XBar, Packet)
#2685 opened Oct 21, 2025 by studyztp Loading…
3
cpu: Enable PcCountTracker in NULL builds cpu General gem5 CPU code (e.g., `BaseCPU`)
#2684 opened Oct 21, 2025 by powerjg Loading…
tests: remove duplicate option on arm boot tests tests gem5's Testing Infrastructure
#2683 opened Oct 21, 2025 by clemdiep Loading…
dev: Temporary fix for X86 board hanging forever dev General gem5 development code. Found in "src/dev"
#2679 opened Oct 21, 2025 by clemdiep Loading…
3
mem-ruby: Add support for CLFLUSH type instructions in MESI Three Level protocol mem-ruby Ruby caches, structures, and protocols
#2675 opened Oct 20, 2025 by AmoghBhagwat Loading…
1
tests: Update resource links to point to azure tests gem5's Testing Infrastructure
#2674 opened Oct 17, 2025 by Harshil2107 Loading…
1
dev: refactor PCI configuration to use RegisterBank dev General gem5 development code. Found in "src/dev"
#2672 opened Oct 17, 2025 by clemdiep Loading…
1
cpu-o3: Instant ROB squash cpu-o3 gem5's Out-Of-Order CPU
#2670 opened Oct 17, 2025 by dhschall Loading…
6
cpu-kvm: added support for hosts with larger page size cpu-kvm gem5's KVM CPU
#2668 opened Oct 16, 2025 by callumgran Loading…
base: Fix memleak in coroutine base Regards gem5's base code. Found in "src/base"
#2666 opened Oct 14, 2025 by powerjg Loading…
3
base,arch-arm,cpu: Cleaning up more headers and tests arch-arm The ARM ISA base Regards gem5's base code. Found in "src/base" cpu General gem5 CPU code (e.g., `BaseCPU`)
#2664 opened Oct 14, 2025 by powerjg Loading…
arch-x86, base-stats: Add MPK feature arch-x86 The X86 ISA base-stats The base gem5 stats code. Found in "src/base/stats"
#2661 opened Oct 13, 2025 by Klaas-Meersman Loading…
3
arch-riscv: fix bugs in pinned registers in vred* instructions arch-riscv The RISC-V ISA
#2659 opened Oct 13, 2025 by Joao-Pedro-Cabral Loading…
1
1
cpu-o3: incorrect vtype and vl generates assert fail in O3 IQ cpu-o3 gem5's Out-Of-Order CPU
#2657 opened Oct 13, 2025 by Joao-Pedro-Cabral Loading…
9
configs, cpu-o3: Implement a distributed InstructionQueue configs gem5's Preprepared Python Configuration scripts. Typically found in "configs" cpu-o3 gem5's Out-Of-Order CPU
#2652 opened Oct 9, 2025 by giactra Loading…
11
cpu-o3: Make space for a pipeline tracer cpu-o3 gem5's Out-Of-Order CPU sim General gem5 Simulation Components
#2651 opened Oct 9, 2025 by giactra Loading…
6
arch-arm, stdlib: Rework the PTW to support a configurable number of outstanding TW arch-arm The ARM ISA stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2650 opened Oct 8, 2025 by giactra Loading…
stdlib: Define a new get_mem_ranges method stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2647 opened Oct 7, 2025 by giactra Loading…
6
arch-arm: Add support for LRCPC instructions arch-arm The ARM ISA
#2632 opened Oct 4, 2025 by pranith Loading…
12
mem-cache: Add unit test for MRU RP mem General Memory Systems (e.g., XBar, Packet)
#2630 opened Oct 2, 2025 by odanrc Loading…
arch-arm: Decouple insts from generated decoder arch-arm The ARM ISA
#2623 opened Oct 1, 2025 by powerjg Loading…
5
ProTip! Updated in the last three days: updated:>2025-10-19.