A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
Pipelined RISC V 32 bit CPU in SystemVerilog
ECE552: Computer Architecture — Fall 2020.
RISC-V RV32I 5-stage pipelined processor implemented in SystemVerilog with RTL design, testbench, and hex-based instruction memory.
Optimized RV32I processor with a 5-stage bypassed pipeline, hardware hazard mitigation, and same-cycle register file forwarding.
Implemented a RISC 5-stage pipeline in C++ and ran a benchmark program to observe a 60% reduction in total execution time between the pipelined and unpipelined design.
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