simple verilog digital circuits sampels (halfAdder, fullAdder, ALSU , ...)

Verilog Code Challenge – KVLSI Kohort 2

All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

Verilog Programs

Digital Logic Design using pen and paper to design with Analog discovery 2, and using Verilog for synthesizing. these are some of my junior year labs for Digital Electronics

VHDL(Verilog Hardware Description Language) is a programming language using which one can simulate hardware circuits

verilog ALU

32-bit ALU design for MIPS.

Digital Design using Verilog

ALU register implementation and added functionalities for shifts

Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.

This repository contains the Verilog design and testbench for a 8x1 Multiplexer. It uses three select lines to choose one of the eight inputs (A0–A7) and drive it to a single output based on the logic expression: Y = S2'S1'S0'A0 + S2'S1'S0A1 + S2'S1S0'A2 + S2'S1S0A3 + S2S1'S0'A4 + S2S1'S0A5 + S2S1S0'A6 + S2S1S0A7

This repository is basic start of building your own processor using verilog (hdl).

Implements a hierarchical 1-to-16 demultiplexer using a 1x2 and two 1x8 demux blocks in Verilog. Directs a single input signal to one of 16 outputs based on select lines. Features: Hierarchical Verilog modules (1x2 and 1x8), Behavioral testbench for all 16 select combinations, Graph-based output verification

Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.

My Solutions to Digital-System-Design Practical Assignments

A collection of Verilog code examples, perfect for beginners or anyone looking to learn Verilog. These examples are based on my homework assignments from my university and include comments and explanations to help you understand the code better. Check out the link below for more information about Verilog!! 👇