Lecture-53
Initialization Control Word 3 ICW3:
This word is read only where there is mode than one 8259A in the
system and one cascading is used in which case SNGL=0. It will load
the 8-bit slave register.
The functions of this register are:
a) In the master mode (either when SP= 1 or in buffered mode
when M/S=1 in ICW4) a 1 is set for each slave in the system.
The master will then release byte 1 of the CALL sequence
(80/85 system only) and will enable the corresponding slave to
release bytes 2 and 3 through the address lines (In 86/88 only
two bytes). The format of ICW3 in this case is,
S7
S6
S5
S4
S3
S2
S1
S0
If Si =1, IR input has a slave and if Si=0, IR input does not have
a slave.
b) In the slave mode (either when
= 0 or if BUF =1 and M/S =0
in ICW4) bits 2-0 identify the slave. The slave compares its
cascade input with these bits and if they are equal bytes 2&3 of
the CALL sequence are released by it on the data bus.
0
ID2
ID1
ID0
The three identification bits ID2, ID1, and ID0 tells the slave 8259A to
which master input, slave is connected.
Initialization Control Word 3 ICW4:
ICW4 is output to only if ICW4 in ICW1 is set to 1. Otherwise
the contents of ICW4 are cleared. The bits in ICW4 are defined as
follows:
SFNM
BUF
MS
AEUI
Bits 7-5: always set to zero.
Bit 4(SFNM): If set to 1, the special fully nested mode is used. This
mode is utilized in system having more than one 8259A. If set to 0, it
is not specific fully nested mode.
Bit 3(BUF): If BUF id set1, the buffered mode is programmed,
otherwise non buffered mode. In this mode
becomes an
enable output and the master/slave determination is by M/S.
Bit 2(M/S): If buffered mode is selected, M/S =1 means the 8259A is
programmed to be a master. M/S =0, means the 8259A is
programmed to be a slave. If BUF=0, M/S has no function.
Bit 1(AEOI):
If AEOI =1, the automatic end of interrupt mode is
programmed.
Bit 0(
): Microprocessor mode, if
system operation, If
operation.
=0, it sets 8259A for 8085
=1, it sets the 8259A for 8086 system
The sequences of routine are,
Operation command words (OCWs):
After the 5259 has been initialized, it is ready to accept interrupt
requests at its ready input lines .during operation the 8259A can be
commanded to operate in different modes using OCWA. These are
three OCWS.
Operation Control Word 1 OCW1: OCW1 sets and cleans the make
bits in the interrupt mask register (IMR).M7 M0 represents the eight
mask bits M=1 indicates the channel is masked (inhibited), M=0
indicates they channel is enabled .OCW1 is output to odd address.
There is no ambiguity in ICW2, ICW3, ICW4 and OCW1 all using the
odd address because the initialization words must always follow
ICW1as detected by the initialization sequence and an output to
OCW1 cannot occur in the middle of this sequence. The format is
given bellow. Masking an IR channel does not affect the other
channel operation.
M7
M6
M5
M4
M3
M2
M1
M0
If Mi = 1 corresponding Interrupt Mask is Set and if Mi = 0
corresponding Interrupt Mask is Reset
OCW2 and OCW3 :( operation control word 2 and 3)
OCW2 & OCW3 are used for controlling the mode of the 8259A
and receiving EOI command OCW2&OCW3 are sent to even address
the format of OCW2&OCW3 are given bellow:
OCW2 (operation control word 2):
SL
EOI 0
L2
L1
L0
R, SL and EOI stands for rotate, set level, and end of Interrupt and
the bit combination of these decides the manner in which ISR bit is
cleared. L2, L1, and L0 decides the interrupt level to be acted upon if
SL bit is made 1.
SL EOI Interrupt Mode
Non-specified EOI command
specified EOI command
Rotates on non-specified EOI
Rotate in AEOI mode (set)
Rotate in AEOI mode (clear)
Rotate on specific EOT command
Set priority command
No-Operation
End of Interrupt
Automatic rotation
specific rotation
Interrupt Level to be acted upon
L2
L1
L0
Interrupt Level
Interrupt 0
Interrupt 1
Interrupt 2
Interrupt 3
Interrupt 4
Interrupt 5
Interrupt 6
Interrupt 7
OCW3 (operation control word 3):
0
ES MH
SMH
RR
RIS
The combination of different bits decides the mode in which Intel
8259A will operate:
ESMM SMM
Operation
No Action
No-Action
Reset Special Mask Mode
Set Special Mask Mode
RR
RIS
Operation
No Action
No-Action
Read Interrupt Request Register on next RD pulse
Read In-service Register on next RD pulse
Operation
No Poll Command
Poll Command
OCW2 is designed from OCW3 by the contents of bit 3 of the
data. Byte if bit 3 is 0, the byte is put in OCW2, and if it is 1, it is put in
OCW3. Both OCW2 &CCW3 are distinguished from ICW1, which
also uses the even address by the contents of bit 4 of the data. If bit 4
is 0,then the byte is put on OCW2 or OCW3 according to bit 3 the bit
is OCW2 only temporally retained by 8259A until the action specified
by them are carried out.
