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Microprocessors and Microcontrollers 59

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Microprocessors and Microcontrollers 59

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harrymainah9
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Microprocessor and Microcontroller

Fig. 2.9 8259 Flow chart of command Words

Operation Command Words (OCWs)


After the Initialization Command Words (ICWs) are programmed into the
8259A, the chip is ready to accept interrupt requests at its input lines. However,
during the 8259A operation, a selection of algorithms can command the 8259A
to operate in various modes through the Operation Command Words (OCWs).

OCW 1
OCW1 sets and clears the mask bits in the interrupt Mask Register (IMR).
M7–M0 represent the eight mask bits. M = 1 indicates the channel is masked
(inhibited), M = 0 indicates the channel is enabled.

OCW 2
R, SL, EOI – These three bits control the Rotate and End of Interrupt modes
and combinations of the two. A chart of these combinations can be found on the
Operation Command Word Format.
L2, L1, L0 – These bits determine the interrupt level acted upon when the
SL bit is active.

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