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Comsats University Islamabad Department of Computer Sciences

This lab report describes digital logic design tasks completed in Xilinx ISE. Students modeled basic logic gates like NOT, OR, NOR, NAND, XOR, and XNOR using both data flow and gate level Verilog. Additionally, they created an equation gate circuit using intermediate wires and modeled it with both a gate level design and data flow equation. The report concludes with a brief analysis of learning Verilog in Xilinx ISE to simulate and model digital circuits.

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102 views8 pages

Comsats University Islamabad Department of Computer Sciences

This lab report describes digital logic design tasks completed in Xilinx ISE. Students modeled basic logic gates like NOT, OR, NOR, NAND, XOR, and XNOR using both data flow and gate level Verilog. Additionally, they created an equation gate circuit using intermediate wires and modeled it with both a gate level design and data flow equation. The report concludes with a brief analysis of learning Verilog in Xilinx ISE to simulate and model digital circuits.

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COMSATS UNIVERSITY ISLAMABAD

Department of Computer Sciences

LAB REPORT 3

Subject:

Digital Logic Design

Submitted to:
Ms. Kiran Nadeem

Submitted by:
Shoaib Naseer SP19-BSE-106

Shazif Rizwan SP19-BSE-105

Sharjeel Shahid SP19-BSE-104

DATE: 3-March-19

In Lab Tasks

DATA FLOW FOR NOT GATE:


module mynot(
input a,
output );
assign b = !a;
endmodule

GATE LEVEL FOR NOT GATE:


module mynot(
input a,
output b
);
not (b,a);
endmodule
DATA FLOW FOR OR GATE:
module myor(
input a,
input b,
output c);
assign c=a|b;
endmodule

GATE LEVEL FOR OR GATE:


module myor(
input a,
input b,
output c );
or (c,a,b);
endmodule
DATA FLOW FOR NOR GATE:
module mynor(
input a,
input b,
output c );
nor (c,a,b);
endmodule
GATE LEVEL FOR NOR GATE:
module mynor(
input a,
input b,
output c );
assign c =!(a|b);
endmodule
DATA FLOW FOR NAND GATE:
module mynand(
input a,
input b,
output c );
assign c =!(a&b);
endmodule
GATE LEVEL FOR NAND GATE:
module mynand(
input a,
input b,
output c );
nand (c,a,b);
endmodule
DATA FLOW FOR XOR GATE:
module myxor(
input a,
input b,
output c);
assign c =(a&(!b))|((!a)&b);
endmodule
GATE LEVEL FOR XOR GATE:
module myxor(
input a,
input b,
output c );
xor (c,a,b);
endmodule
DATA FLOW FOR XNOR GATE:
module myxnor(
input a,
input b,
output c );
assign c =(a|(!b))&((!a)|b);
endmodule
GATE LEVEL FOR XNOR GATE:
module myxnor(
input a,
input b,
output c );
xnor (c,a,b);
endmodule
POSTLAB TASKS

GATE LEVEL FOR EQUATION GATE:


module equation(
input a,
input b,
input c,
output f );
wire n,m,w1,w2;
not (n,a);
not (m,c);
and (w1,n,b);
and (w2,b,m);
or (f,a,w1,w2);
endmodule
DATA FLOW FOR QUATION GATE:
module equation (
input a,
input b,
input c,
output f);
assign f= (a)|((!a)&b)|(b&(!c));
endmodule

Critical Analysis
In this lab, we learned Verilog (Hardware Description Language) in Xilinx ISE. It is used to
simulate or model digital systems and is commonly used to design and verify digital circuits.

In the second part we used Xilinx ISE which is a verification and simulation tool for Verilog.

We used this system to test various logic gates.

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