Chapter 3

Gate-Level Minimization
Boolean Algebra and Logic Gate

• 3.1 Introduction
• 3.2 The Map Method
• 3.3 Four‐Variable K-Map
• 3.4 Product‐of‐Sums Simplification
• 3.5 Don’t‐Care Conditions
• 3.6 NAND and NOR Implementation
• 3.7 Other Two‐Level Implementations
• 3.8 Exclusive‐OR Function
3.1 Introduction

• Gate-level minimization refers to the design task of finding an optimal gate-

level implementation of Boolean functions describing a digital circuit.
• This task is well understood but is difficult to execute by manual methods when
the logic has more than a few inputs.
• Fortunately, computer-based logic synthesis tools can minimize a large set of
Boolean equations efficiently and quickly.
• Nevertheless, it is important that a designer understand the underlying
mathematical description and solution of the problem.
3.2 The Map Method

• The complexity of the digital logic gates

• The complexity of the algebraic expression
• Logic minimization
• Algebraic approaches: lack specific rules
• The Karnaugh map
• A simple straight forward procedure
• A pictorial form of a truth table
• Applicable if the # of variables < 7
• A diagram made up of squares
• Each square represents one minterm
3.2 The Map Method -- Review of Boolean Function

• Boolean function
• Sum of minterms
• Sum of products (or product of sum) in the simplest form
• A minimum number of terms
• A minimum number of literals
• The simplified expression may not be unique
3.2 The Map Method -- Two-Variable K-Map

• A two-variable map
• Four minterms
• x' = row 0; x = row 1
• y' = column 0; y = column 1
• A truth table in square diagram
• Fig. 3.2(a): xy = m3
Figure 3.1 Two-variable Map
• Fig. 3.2(b): x+y = x'y+xy' +xy = m1+m2+m3

Figure 3.2 Representation of functions in the map

3.2 The Map Method

• Rules for K-Map Pairing & Grouping

• In choosing adjacent squares in a map, we must ensure that

• (1) all the minterms of the function are covered when we combine the squares,
• (2) the number of terms in the expression is minimized, and
• (3) there are no redundant terms (i.e., minterms already covered by other terms).
3.2 The Map Method -- A Three-variable Map

• A three-variable map
• Eight minterms
• The Gray code sequence
• A Gray Code represents numbers using a binary encoding scheme that
groups a sequence of bits so that only one bit in the group changes from
the number before and after.
• Any two adjacent squares in the map differ by only on variable
• Primed in one square and unprimed in the other
• e.g., m5 and m7 can be simplified
• m5+ m7 = xy'z + xyz = xz (y'+y) = xz

• m0 and m2 (m4 and m6) are adjacent

• m0+ m2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z'
• m4+ m6 = xy'z' + xyz' = xz' (y'+y) = xz'

Figure 3.3 Three-variable Map

3.2 The Map Method -- A Three-variable Map -- Example

• Example 3.1: simplify the Boolean function F(x, y, z) = S(2, 3, 4, 5)

• F(x, y, z) = S(2, 3, 4, 5) = x'y + xy'
3.2 The Map Method -- A Three-variable Map -- Example

• Example 3.2: simplify F(x, y, z) = S(3, 4, 6, 7)

• F(x, y, z) = S(3, 4, 6, 7) = yz+ xz'
3.2 The Map Method -- A Three-variable Map -- Example

• Consider four adjacent squares

• 2, 4, and 8 squares
• m0+m2+m4+m6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) = x'z' + xz‘ = z'
• m1+m3+m5+m7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z + xz = z

• Example 3.3
• Simplify F(x, y, z) = S(0, 2, 4, 5, 6)
• F(x, y, z) = S(0, 2, 4, 5, 6) = z'+ xy'
3.2 The Map Method -- A Three-variable Map -- Example

• Example 3.4: let F = A'C + A'B + AB'C + BC

a) Express it in sum of minterms.
b) Find the minimal sum of products expression.
Ans:
F(A, B, C) = S(1, 2, 3, 5, 7) = C + A'B
3.3 Four‐Variable K-Map

• The map
• 16 minterms
• Combinations of 2, 4, 8, and 16 adjacent squares
3.3 Four‐Variable K-Map -- Example

• Example 3.5: simplify F(w, x, y, z) = S(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

3.3 Four‐Variable K-Map -- Example

• Example 3-6: simplify F = ABC + BCD + ABCD + ABC

3.3 Five-Variable Map

• Map for more than four variables becomes complicated

• Five-variable map: two four-variable map (one on the top of the other).
3.4 Product‐of‐Sums Simplification

• Approach #1
• Simplified F' in the form of sum of products
• Apply DeMorgan's theorem F = (F')'
• F': sum of products → F: product of sums
• Approach #2: duality
• Combinations of maxterms (it was minterms)
• M0M1 = (A+B+C+D)(A+B+C+D') = (A+B+C)+(DD') = A+B+C

CD
AB 00 01 11 10
00 M0 M1 M3 M2
01 M4 M5 M7 M6
11 M12 M13 M15 M14
10 M8 M9 M11 M10
3.4 Product‐of‐Sums Simplification -- Example 3.7

 Example 3.8: simplify F = S(0, 1, 2, 5, 8, 9, 10) into (a) sum-of-products form,

and (b) product-of-sums form:

a) F(A, B, C, D)= S(0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D

b) F' = AB+CD+BD'
» Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D)
» Or think in terms of maxterms

Figure 3.14 Map for Example 3.8, F(A, B, C, D)= S(0, 1, 2, 5, 8, 9, 10) = B'D'+B'C'+A'C'D
3.4 Product‐of‐Sums Simplification -- Example 3.7 (cont.)

• Gate implementation of the function of Example 3.7

Sum-of products form Product-of sums form

3.4 Product‐of‐Sums Simplification -- Sum-of-Minterm Procedure

• Consider the function defined in Table 3.1.

• In sum-of-minterm:

F ( x, y, z ) =  (1,3, 4,6)

• In sum-of-maxterm:

F ( x, y, z ) = (0,2,5,7)

• Taking the complement of F

F ( x, y, z ) = ( x + z)( x + z )
3.4 Product‐of‐Sums Simplification -- Sum-of-Minterm Procedure

• Consider the function defined in Table 3.1.

• Combine the 1’s:

F ( x, y, z ) = xz + xz

• Combine the 0’s :

F ( x, y, z ) = xz + xz

Figure 3.16 Map for the function of Table 3.1

3.5 Don’t‐Care Conditions

• The value of a function is not specified for certain combinations of variables

• BCD; 1010-1111: don't care
• 1010, 1011, 1100, 1101, 1110, 1111
• These six invalid codes are don’t cares as far as we are concerned with BCD.
• The don't-care conditions can be utilized in logic minimization
• Can be implemented as 0 or 1
• Example 3.8:
• simplify F(w, x, y, z) = S(1, 3, 7, 11, 15)
• which has the don't-care conditions d(w, x, y, z) = S(0, 2, 5).
3.5 Don’t‐Care Conditions -- Example 3.8 (cont.)

• F = yz + w'x'; F = yz + w'z
• F = S(0, 1, 2, 3, 7, 11, 15) ; F = S(1, 3, 5, 7, 11, 15)
• Either expression is acceptable
3.6 NAND and NOR Implementation

• NAND gate is a universal gate

• Can implement any digital system

Figure 3.18 Logic Operations with NAND Gates

3.6 NAND and NOR Implementation -- NAND

• Two graphic symbols for a NAND gate

Figure 3.19 Two Graphic Symbols for NAND Gate

3.6 NAND and NOR Implementation -- Two-Level Implementation

• The implementation of Boolean functions with NAND gates requires that the functions be in sum-of-
products form.
• To see the relationship between a sum-of-products expression and its equivalent NAND
implementation, consider the logic diagrams drawn in Fig. 3.18 . All three diagrams are equivalent
and implement the function F = AB + CD
3.6 NAND and NOR Implementation -- Two-Level Implementation

• EXAMPLE 3.9
• Implement the following Boolean function with NAND gates: F (x, y, z) = (1, 2, 3, 4, 5, 7)
3.6 NAND and NOR Implementation -- Multilevel NAND Circuits

• Boolean function implementation

• AND-OR logic → NAND-NAND logic
• AND → AND + inverter
• OR: inverter + OR = NAND
• For every bubble that is not compensated by another small circle along the same line, insert an
inverter.

Figure 3.22 Implementing F = A(CD + B) + BC

3.6 NAND and NOR Implementation -- NAND Implementation

Figure 3.23 Implementing F = (AB +AB)(C+ D)

3.6 NAND and NOR Implementation -- NOR Implementation

• NOR function is the dual of NAND function.

• The NOR gate is also universal.

Figure 3.24 Logic Operation with NOR Gates

3.6 NAND and NOR Implementation -- NOR Implementation

• Two Graphic Symbols for a NOR Gate

Figure 3.25 Two Graphic Symbols for NOR Gate

Example: F = (A + B)(C + D)E

Figure 3.26 Implementing F = (A + B)(C + D)E

3.6 NAND and NOR Implementation -- NOR Implementation

Example: F = ( AB +A B )( C + D )

3.7 Other Two‐Level Implementations

• Wired logic
• A wire connection between the outputs of two gates
• Open-collector TTL NAND gates: wired-AND logic
• The NOR output of ECL gates: wired-OR logic
F = ( AB )  (CD ) = ( AB + CD ) = ( A + B)(C  + D) AND-OR-INVERT function
F = ( A + B ) + (C + D ) = [( A + B )(C + D )] OR-AND-INVERT function

Note:
A wired-logic gate does not produce a
physical second-level gate, since it is just
wire connection.
3.7 Other Two‐Level Implementations

Degenerated & Non-Degenerated Forms

• DEGENERATE logic gate combinations are the logic combinations that effectively generates a
SINGLE logic.
• Any 2 level implementation is in degenerate form, if the two level gates degenerate into a single logic
operation.

• NON-DEGENERATE In contrast with DEGENERATE logic the logic combinations does not
generate a SINGLE logic.
• It always generates
• SUM of PRODUCTS
OR
• PRODUCT of SUMS
3.7 Other Two‐Level Implementations

Degenerated & Non-Degenerated Forms

• 16 possible combinations of two-level forms
• Eight of them: degenerate forms = a single operation
• AND-AND, AND-NAND, OR-OR, OR-NOR, NAND-OR, NAND-NOR, NOR-AND, NOR-NAND.
• The eight non-degenerate forms
• AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-NAND, AND-NOR.
• AND-OR and NAND-NAND = sum of products.
• OR-AND and NOR-NOR = product of sums.
• NOR-OR, NAND-AND, OR-NAND, AND-NOR = ? Logic Gate Expression
AND X . Y
OR X + Y
NAND (X . Y)′
NOR (X + Y)′
XOR X . Y′ + X′. Y
XNOR X . Y + X′. Y′
3.7 Other Two‐Level Implementations

Degenerated Forms
• AND-AND, OR-OR, AND-NAND, OR-NOR, NAND-OR, NOR-AND, NOR-NAND, NAND-NOR
combinations are degenerate because they will result in a single operation effectively.

• Here F will be A.B.C.D (effectively a single level logic that can be performed with a 4-input
AND gate only)
3.7 Other Two‐Level Implementations

Non-Degenerated Forms
• AND-OR, OR-AND, NAND-NAND, NOR-NOR, NOR-OR, NAND-AND, OR-NAND, AND-NOR.

AND-OR logic

• F effectively gives you : (A.B + C.D) which is a two-level logic, and you cannot, by any means,
optimize this combination to a single level logic (like you could have with DEGENERATE ones)
and you cannot use only 1 gate type with multiple inputs as well.
3.7 Other Two‐Level Implementations

AND-OR-INVERT (AOI) Implementation

• NAND-AND = AND-NOR = AOI
• F = (AB+CD+E)'
• F' = AB+CD+E (sum of products)

Figure 3.29 AND-OR-INVERT circuits, F = (AB +CD +E)

3.7 Other Two‐Level Implementations

OR-AND-INVERT (OAI) Implementation

• OR-NAND = NOR-OR = OAI
• F = ((A+B)(C+D)E)'
• F' = (A+B)(C+D)E (product of sums)

Figure 3.30 OR-AND-INVERT circuits, F = ((A+B)(C+D)E)'

3.7 Other Two‐Level Implementations

Tabular Summary and Examples

• Example: F = x'y'z'+xyz'
• F' = x'y+xy'+z (F': sum of products)
• F = (x'y+xy'+z)’ (F: AOI implementation)
• F = x'y'z' + xyz’ (F: sum of products)
• F' = (x+y+z)(x'+y'+z) (F': product of sums)
• F = ((x+y+z)(x'+y'+z))' (F: OAI)
3.7 Other Two‐Level Implementations
3.8 Exclusive‐OR Function

• Exclusive-OR (XOR)
• xy = xy'+x'y
• Exclusive-NOR (XNOR)
• (xy)' = xy + x'y'
• Some identities
• x0 = x
• x1 = x'
• xx = 0
• xx' = 1
• xy' = (xy)'
• x'y = (xy)'
• Commutative and associative
• AB = BA
• (AB) C = A (BC) = ABC
3.8 Exclusive‐OR Function -- Implementations

• Implementations
• (x'+y')x + (x'+y')y = xy'+x'y = xy
3.8 Exclusive‐OR Function -- Odd Function

• ABC = (AB'+A'B)C' +(AB+A'B')C = AB'C'+A'BC'+ABC+A'B'C = S(1, 2, 4, 7)

• XOR is an odd function → an odd number of 1's, then F = 1.
• XNOR is an even function → an even number of 1's, then F = 1.
3.8 Exclusive‐OR Function

• Four-variable Exclusive-OR function

3.8 Exclusive‐OR Function -- Parity Generation and Checking

• Exclusive-OR functions are very useful in systems requiring error detection and
correction codes.
• Parity Generation and Checking
• A parity bit: P = xyz
• Parity check: C = xyzP
• C=1: one bit error or an odd number of data bit error
• C=0: correct or an even # of data bit error
3.8 Exclusive‐OR Function -- Parity Generation and Checking

• A parity bit: P = xyz

• Parity check: C = xyzP
• C=1: one bit error or an odd number of data bit error
• C=0: correct or an even # of data bit error
 End of Chapter 3

Gate-Level Minimization