A SUMMER INTERNSHIP REPORT

On
Internship Module

Signal Processing Using TCAD

Submitted for partial fulfillment

of

B. Tech. in

ELECTRONICS AND COMMUNICATION

ENGINEERING

SUBMITTED TO SUBMITTED BY

Dr. Koushik Midya Arnav Singhal

Asst. Prof. ECE Department 1900270310037
3rd year ECE 1

Ajay Kumar Garg Engineering College, Ghaziabad

27th Km Stone, Delhi-Hapur Bypass Road, Adhyatmik Nagar, Ghaziabad-201009
Dr. A. P. J. Abdul Kalam Technical University, Lucknow
DECEMBER 2021
 Acknowledgement
I want to express my sincere gratitude and thanks to Prof. (Dr.) P. K. Chopra
(H.O.D., ECE Department and Training & Placement Cell), Ajay Kumar
Garg Engineering College, Ghaziabad for granting me permission for my
industrial training in the field of “Area of Training / Specialization”.
I express my sincere thanks to Dr. Koushik Midya Sir for his cooperative
attitude and consistence guidance, due to which I was able to complete my
training successfully.
Finally, I pay my thankful regard and gratitude to the team members and
technicians of “Training Resource Company/Organization” and Ajay
Kumar Garg Engineering College, Ghaziabad for their valuable help,
support, and guidance.

ARNAV SINGHAL

1900270310037

3rd Year ECE-1

 TABLE OF CONTENTS

Chapter 1. Introduction to TCAD 1-4

1.1 What is TCAD? 1
1.2 Uses of TCAD 2-3
1.3 Visual TCAD 4

Chapter 2. Introduction to Major toolboxes in TCAD 4-6

2.1 Graphical User Interface 3
Chapter 3. Features of Visual TCAD 7-10
Chapter 4. Project Undertaken 11-15

REFERENCES
[1]http://www.tsmc.com/english/dedicatedFoundr
y/ technology/mtm.htm
[2] Chaudhry A (2012) Alternate Materials for
Nanoscale MOSFETs . J Elec Electron 1:e105.
doi:10.4172/2167-101X.1000e105
[3] M. J. Palmer et al.: Effective mobilities in
pseudomorphic Si/SiGe/Si p-channel metaloxidesemiconductor
field-effect transistors with thin
silicon capping layers. Applied Physics Letters,
78, p.1424- 1426, 2001.
[4] T. E. Whall and E. H. C. Parker, “Si
Geheterostructures for CMOS technology”, Thin
Solid Films 367 250-259, 2000.
[5] D. J. Paul, Silicon Germanium
Heterostructures in Electronics
[6] Ouellette, Jennifer. "Silicon–Germanium
Gives Semiconductors the Edge"
[7] http://www.cogenda.com/article/applications
Chapter 1: Introduction To TCAD
Technology computer-aided design (technology CAD or TCAD) is a branch
of electronic design automation that models semiconductor fabrication and
semiconductor device operation. The modelling of the fabrication is termed
Process TCAD, while the modelling of the device operation is termed Device
TCAD. Technology Computer-Aided Design (TCAD) refers to the use of
computer simulations to develop and optimize semiconductor process
technologies and devices. Synopsys TCAD offers a comprehensive suite of
products that includes industry-leading process and device simulation tools, as
well as a powerful graphical user interface (GUI) driven simulation
environment for managing simulation tasks and analysing simulation results. In
addition, Synopsys TCAD provides tools for interconnect modeling and
extraction, providing critical parasitic information for optimizing chip
performance. 

•   Synopsys TCAD is the industry leader in 3D technology modeling

•   Provides integrated simulation environment for Design Technology Co-
Optimization
•   Delivers production-proven modeling solutions for Logic, Memory, Power,
and CIS applications
•   Offers smart technology modeling enables cost and time savings in
pathfinding, development, and production ramping of semiconductor
technologies
Uses Of TCAD

Atomic-Scale Modeling
QuantumATK simulates the properties and transport mechanisms of novel
materials and device structures, enabling the down-selection of promising materials
for further exploration and the TCAD-level simulation of advanced devices before
wafer-based data is available. Sentaurus Materials Workbench provides a link
between QuantumATK output and TCAD models implemented in Sentaurus
simulators.

Process Simulation
Sentaurus Process is the industry standard for simulating the fabrication steps of
semiconductor processes, ranging from silicon-based logic, memory, power, and
CIS technologies to SiC-based technologies. Sentaurus Process supports the
modeling of implantation, diffusion and dopant activation, thermal oxidation,
mechanical stress, and epitaxial growth. Sentaurus Topography supports the
modeling of topographical steps including etching, deposition, CMP, and
electroplating.
Process Emulation
Sentaurus Process Explorer is a fast 3D process emulator used to identify and
correct process integration issues during technology development. Sentaurus
Process Explorer produces highly realistic 3D representations of process structures
using GDSII mask data and a process recipe as input. Sentaurus Process Explorer
is linked to the Synopsys TCAD simulators, such as Raphael FX, to enable the
high accuracy RC extraction in Design Technology Co-Optimization (DTCO)
applications.

Device Simulation
Sentaurus Device is the industry standard for simulating the electrical
characteristics of silicon-based and compound semiconductor devices as a response
to external electrical, thermal, or optical boundary conditions. Advanced physical
models for quantum effects, ballistic transport, tunnelling processes, stress
engineering, hot carrier effects, and other transport phenomena support the
optimization of state-of-the-art devices ranging from advanced logic and memory
to analog, power and optoelectronics devices.

Structure Editing
Sentaurus Structure Editor is a device structure editor used to create structures for
device simulation when process simulation is not required. Sentaurus Structure
Editor uses geometric primitives powered by the ACIS® geometry kernel to render
complex device shapes. A graphical user interface serves as the front end for mesh
generation engines available in Sentaurus Process and Sentaurus Device. The
Sentaurus Structure Editor command language recreates the device structure in
batch mode as part of a simulation flow.
Interconnect Simulation
Interconnect simulation tools address the electrical and reliability performance of
middle-of-line and back-end-of-line interconnect structures. Raphael FX is the
industry gold-standard 3D field solver for extracting the resistance and capacitance
of detailed interconnect structures, SRAM cells, and standard cells in DTCO.
Centaurus Interconnect simulates the reliability of interconnect structures based on
the mechanical stress generated through thermal processing and externally applied
forces.

TCAD Environment
Centaurus Workbench is a complete graphical environment for creating, managing,
executing, and analysing TCAD simulations. Its intuitive graphical user interface
(GUI) allows users to efficiently navigate and automate the typical tasks associated
with running TCAD simulations such as managing the information flow, including
pre-processing of user input files, parameterizing projects, setting up and executing
tool instances, optimization, and visualizing results. Centaurus Visual is an
advanced visualization tool for TCAD data. It includes extensive capabilities for
plotting and interactively manipulating by data as well as 2D and 3D TCAD
structures.
VisualTCAD: User Graphical Interface
for Device Simulation
The tool is design by the Cogenda semiconductors, Singapore. As per the tool is used for
Device Modeling, Simulation and Characterization of the Device (transistors and diodes) are
done using different methods. Analytical method is used for modeling which consists of
closed form equations obtained using spice. Experimental method is required for
characterization. Numerical methods which are based on the concept of 2D/3D meshing can
be adopted for conducting simulation studies which requires Technology CAD. Different
TCAD device simulators are MEDICI, SILVACO (ATLAS), SYNOPSIS (SENTAURAS),
and COGENDA (Visual TCAD). Among this 2D/3D simulation is possible using
COGENDA TCAD.
Cogenda TCAD consists of Genius powerful simulator and Visual TCAD interactive GUI in
which 2D structures and 3D structures can be created. Circuit simulation is also available in
this tool. Core features are provision for Advanced device modeling, Circuit schematic
capturing, easy device simulation control, Versatile device visualization, Syntax highlighted
text editor, Spreadsheet and X‐Y Plots for 2D along with Z direction if used in 3D. Multiple
analysis modes such as DC / Transient / AC simulation and optical simulation are there in the
tool itself. Advanced setup such as boundary conditions, material parameters, physical
models are also available. By using Visual TCAD, one can gain clearer image of
understanding semiconductor devices physics and Microelectronics
2D device structures can be drawn and there are 2 methods for 3D device drawing. Either 2D
structure can be drawn and extended to Z Axis or direct 3D structure can be formed using
deck (code) format. In extended 3D method, meshes in the Z direction is automatically
generated whereas there is provision for defining meshes in X,Y, and Z direction in deck
scheme which makes it more accurate and interactive .
Various steps followed for device simulation are:
 Define X,Y, and Z mesh

 Define regions and corresponding materials

 Define doping Profile

 Apply models
 Apply bias

 Export the output file

Introduction To Major Toolboxes in TCAD.

Using the Graphical User Interface

Visual TCAD is the integrated graphical user interface of the Genius device simulation package.
1. To start Visual TCAD in Linux.

 Open the terminal or Press [ctrl+alt+t]

 Type Visual TCAD or the corresponding alias name

 Fig 1: Visual TCAD GUI win

2. To draw new structure.

 Click on file

 New file

 Device drawing

3. To write Deck file (code)

 Click on file

 New file

 Text document

4. To do Device simulation
 Click on file

 New file

 Device simulation

5. To Draw circuit schematic

 Click file

 New file

 Circuit schematic
The version number of the release can be checked by clicking the > menu > Help > about. The
version number will be coming in a dialog box as shown below

Fig 2: dialogue box showing version number

Features of Visual TCAD

1. Advanced Device Drawing Tools

Fig 3. A demo NMOS device with meshed network

2. Easy Simulation Setup

 Fig 4. A demo NMOS device with simulation workbench

3. Versatility in Device Visualization

Fig 5.visualization of NMOS demo after simulation

Comparative Study of SiGe MOSFET with Single
Substrate MOSFET Using Visual TCAD

Abstract
A comparative study of SiGe based MOS transistor with single Si and Ge based MOS
transistors
has been investigated. The objective of this study is to analyse the performance of SiGe
MOSFET
which shows some significantly better electrical characteristics as compared to the silicon and
Germanium channel MOSFET’s. Design, Simulation, and analysis of transistors has been
performed with the help of Visual TCAD.
Keywords: SiGe, NMOS, Visual TCAD, I-V characteristics.

INTRODUCTION

According to the predictions of International Technology Roadmap of Semiconductors

(ITRS),there is an intensive need for the replacement of the silicon as a substrate material in a
nanoscale MOSFET. Germanium, SiGe, III-V materials or Grapheme have been seen as a
potential replacement to silicon. This is required because the Moore’s law follow in the sub
nanoscale technologies. Recently, the global semiconductor industry is seeing a new trend
called “More-than-Moore” (MtM), where added values to devices are provided by
incorporating functionalities that do not necessarily scale according to Moore's Law.
According to the Moore's Law number of transistors on a chip will double every 18 months.
However, Moore's Law will one day face its ultimate limitation, due to the physical
properties of the chip. In electronics chip fabrication the key focus is packing more transistors
on a chip to provide better performance and power which develops MtM technology on the
top of the Moore's Law technologies to provide further values to semiconductor chips. We
know that the vertical and horizontal electric fields seriously affected the mobility in the
MOS device at the nanometre scale. The reduction in
the carrier mobility reduces the drain current and eventually the speed of the transistor. The
main advantage of using these alternate materials is to increase the carrier mobility in a
MOSFET.[1-3]. It is well known that silicon devices dominate the microelectronics industry.
It plays 98% of sales in the global semiconductor market, largely because of their low
manufacturing cost. However, the driving force behind today’s growth in high-speed
optical networking and inexpensive, lightweight personal-communications devices are not
silicon but silicon–germanium (SiGe). This technology increases operating speed,
reduces electronic noise, lowers power consumption, supports higher levels of integration,
and, thus, enables the design of more functional components on a chip. SiGeis a
revolutionary process technology in which the electrical properties of silicon are improved
with germanium to make the chips operate more efficiently. Introducing germanium into the
base layer of an otherwise all-silicon bipolar transistor improves operating frequency, current,
noise, and power capabilities. It acts a bridge between low cost, low-power, low-frequency
silicon chips and high-cost, high-power, high-frequency made from class III-V
semiconductor materials such as gallium arsenide and indium phosphide.
Bell Laboratories discovered that SiGe has a smaller band gap than conventional silicon,
making it useful for building transistors that leads the design of heterostructures[4,5]. One of
the advantages of SiGe technology that maintains state-of-the-art silicon processing. SiGe
processing is relatively simple as compared to highspeed semiconductors made of two or
more
materials because silicon and germanium have similar chemical and physical properties.
Ordinary silicon does not operate at frequencies above a few gigahertz, so it has drawback to
use in higher-speed wireless telecommunications devices. In contrast to silicon-based chips,
SiGe semiconductors provide higher speed. SiGe or silicon-germanium, is a general term for
the alloy Si1−xGex which consists of any molar ratio of silicon and germanium.

DESIGN AND SIMULATION

The general processes to design 180nm MOSFET involving simulation of fabrication

process, structure and mesh and electrical testing. the first step for designing the MOSFET is
to draw the ‘device drawing’ using VisuallTCAD , further meshing is done. The doping
profiles used in the designed MOSFET is listed as below
The designed structure of MOSFET and the material used in structure are shown in

Figure 1: Mesh structure of MOSFET

 Figure 2: Basic Structure of MOSFET

RESULT AND ANALYSIS

We have analysed and simulated the output drain current of Si, Ge base MOSFET and SiGe
MOSFET for variable mole fraction (Si1−xGex MOSFET). The Simulated result are as follows
: (x represent the mole fraction of germanium in the result).
Table 1: Drain Current of Si/Ge MOSFET and SiGe with
different mole fraction at fix gate voltage

The length of the SiGe region is equal to the channel length L. the depth is given by the depletion
layer width, Wd , to be determined later. As the normal component of the electric field changes by a
factor of / ≈ 3 SiGe ox ε ε across the silicon-oxide boundary AF [46]. To eliminate this boundary
condition so that ψ and its derivatives are continuous, the oxide is replaced by an equivalent region
of the same dielectric constant as SiGe, but with the thickness equal to3 ox t . This preserves the
capacitance and allows the entire rectangular region to be treated as a homogeneous material of
dielectric constant SiGe ε . The drawback is that it may cause some error in tangential field, whose
magnitude does not change across the silicon-oxide boundary. In the equivalent structure, the
tangential field apparently experiences a thicker-than-actual oxide. The errors are expected to be
smaller when the gate oxide is thin compared to the silicon depletion depth Wd so that the oxide
field is dominated by its normal component.
Table 2: Drain Current of Si/Ge MOSFET and SiGe with
different mole fraction at fix drain voltage
From the simulated result we can see that for different value of mole fraction of
SiGe the darin current is higher than the Si and Ge base MOS transistor

CONCLUSION

The effect of mole fraction of SiGe on the characteristic curve of drain-source current verse
gate voltage/ drain voltage in designed SiGe MOSFETs has been studied. By varying the
mole fraction of SiGe without altering other parameters the drain current value is noted. From
the above simulation we can conclude that designed SiGe MOSFET provide better drain and
transfer characteristics in comparison of Si and Ge base MOS transistors. The work presented
here shows the performance of a 0.25µm strained Si/SiGe nchannel MOSFET. In this work, the
behavior of MOSFET is observed with the help of OrCAD simulation software. The effect of Ge
concentration in strained Si/SiGe channel is seen. SiGe band gap is affected more by Ge introduction
in SiGe compared to that of strained silicon band gap. Strain generated in channel increases the
mobility of electrons in MOSFET that enables that device to be used for high-speed operation and
due to low threshold voltage, it also takes less power for their operation. Hence one can say that this
strained Si/SiGe n-channel MOSFET can have tremendous applications in modern communication
equipment and biomedical field. The present work can be extended to a device with different doping
profile concentrations. The speed of operation can be enhanced by use of other combination of alloy
in the channel. Hence one can analyze the current behavior of the device with different alloy
combinations. Analytical model for obtaining current can also be done to validate the simulated
results. Performance of a device with high dielectric constants may also be evaluated by using this
model.