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Digital Trainer Kit

BREADBOARD

The breadboard consists of two terminal strips and two bus strips (often broken in the
centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That
is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips
are used primarily for power supply connections, but are also used for any node requiring a large
number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of
the centre gap. Each row of 5 contacts is a node.

You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22-26 gauge wire. There are
wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power
supply connections to separate bus strips.

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The 5V supply MUST NOT BE EXCEEDED since this will damage the Ics (Integrated
circuits) used during the experiments. Incorrect connection of power to the ICs could result in them
exploding or becoming very hot - with the possible serious injury occurring to the people working
on the experiment! Ensure that the power supply polarity and all components and connections are
correct before switching on power.

Building the Circuit:

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring
a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus
strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction
with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the
chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire between corresponding
pins of the chips on your breadboard. It is better to make the short connections before the longer
ones. Mark each connection on your schematic as you go, so as not to try to make the same
connection again at a later stage.
7. Get one of your group members to check the connections, before you turn the power on.
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8. If an error is made and is not spotted before you turn the power on. Turn the power off
immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and
return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as it was before you
started.

Common Causes of Problems:

1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the
start of the experiment and return them to their proper place after you have finished the experiment.
Please inform the demonstrator or technician ifyou locate faulty equipment. If you damage a chip,
inform a demonstrator, don't put it back in the box of chips for somebody else to use.

Example Implementation of a Logic Circuit:

Build a circuit to implement the Boolean function F = /(/A./B), please note that the notation
/A refers to . You should use that notation during the write-up of your laboratory experiments.

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Fig 2. The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small indented circle above
the first pin of the chip. Place your chips in the same direction, to save confusion at a later stage.
Remember that you must connect power to the chips to get them to work.

DIGITAL IC’s

IC 7400 NAND GATE

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IC 7402 NOR GATE

IC 7432 OR GATE

IC 7408 AND GATE

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IC 7486 EX-OR GATE

IC 7404 NOT GATE

IC 7411 THREE INPUT NAND GATE

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IC 7476 Dual J/K M/S Flip Flop

JK FLIP-FLOP
K1 Q1 Q1' GND K2 Q2 Q2' J2

16 15 14 13 12 11 10 9

IC7476

1 2 3 4 5 6 7 8

CLK1 PR1 CLR1 J1 VCC CLK2 PR2 CLR2

D- FLIP-FLOP

VCC 2Q' 2D 2CLK 2S' 2Q 2Q'

14 13 12 11 10 9 8

I C 7 4 7 4

1 2 3 4 5 6 7

1R' 1D 1CLK 1S' 1Q 1Q' GND

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EX NO: 1 TRUTH TABLE VERIFICATION OF LOGIC GATES

DATE:

AIM:
To verify the truth tables of AND, OR, NOT, NAND, NOR gates and EXOR gates using
IC’s

APPARATUS REQUIRED:

S.NO COMPONENTS SPECIFICATION QUANTITY

1 AND GATE IC 7408 1
2 OR GATE IC 7432 1
3 NOT GATE IC 7404 1
4 NAND GATE IC 7400 1
5 NOR GATE IC 7402 1
6 EXOR GATE IC 7486 1
7 DIGITAL POWR SUPPLY (0-5)V 1
8 DIGITAL TRAINER (0-12)V 1

THEORY:
Logic Gates are the basic elements of Digital systems and design

GATE- is a two way operation [BINARY] open Gate or Closed Gate

We can assign any of these actions as Asserted state and other as NOT Asserted depending
on the type of Active State, we can Assign Asserted state as Logic 1[+ Ve logic ] and Logic 0
[-Ve logic ].Similarly we can Assign NOT asserted State as Logic 0 or Logic 1, again depending
on the type of Boolean logic used or applied

AND gate

An AND gate has two or more inputs and one output .This performs logical multiplication. The
output of an AND Gate is 1 when all the inputs are equal to 1 .Output of an AND gate is 0, when
at least one of the inputs is 0.
Important, easy & unique way to remember an AND gate is that – Only all the inputs are asserted,
the output is asserted

OR Gate

An OR gate has two or more inputs and one output. This performs logical addition.
The output of an OR Gate is 0, when both the inputs are 0 .The output of an or gate is 1 when at
least one of the inputs is 1. Important, easy & unique way to remember an OR gate is that –If either
of all the inputs are asserted, the output is asserted

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INVERTER or NOT Gate

It performs an Inversion or complementation operation .it has one input and one output. The output
of NOT gate is 1 ,if the input is 0 or vice versa .The presence of a small circle ,known as bubble
,always denotes inversion in digital Circuits.

NAND Gate

The NOT-AND operation is known as the NAND operation .The output of the NAND Gate
assumes 1 level ,if atleast one of the inputs is at 0 level .The NAND Gate is also called as universal
gate because by using the NAND gate we can implement all other gates .

NOR Gate

The NOT-OR operation is known as the NOR operation .The output of the NOR Gate assumes 1
level, if both the inputs are high .The NOR Gate is also called as universal gate because by using
the NOR gate we can implement all other Logic Gates

EX-OR Gate

The outputs of an EX-OR Gate assumes the state 1,if the inputs are indifferent .It assumes state 0
,when both the inputs are same .

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LOGIC DIAGRAM AND ITS DICRETE COMPONENTS

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PROCEDURE:

1. Connect the components as per the given circuit.

2. Apply the binary bits as per the truth table.
3. Verification of glowing LED confirms the required data in the truth table.

QUESTIONS:

1. What do you mean by Logic Gates?

2. What are the applications of Logic Gates?
3. What is Truth Table?
4. Why we use basic logic gates?
5. When the output of NAND, AND, OR, NOR Gate is HIGH?
6. When the output of NAND, AND, OR, NOR Gate is LOW?
7. Develop a Truth Table for three-input AND, OR gate?
8. Which Logic gate acts as a Comparator?
9. What is the basic function of inverter?
10. Which Logic Gates is referred to as Universal Gates& Why?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the truth table for AND, OR, NOT, NAND, NOR, EXOR gates are verified.

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EX No: 2 VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC

DATE: GATES

AIM:
To implement and Verify Boolean theorem and the given Boolean functions using digital
logic gates .

APPARATUS REQUIRED:

S.NO COMPONENTS SPECIFICATION QUANTITY

1 AND GATE IC 7408 1
2 OR GATE IC 7432 1
3 NOT GATE IC 7404 1
4 NAND GATE IC 7400 1
5 NOR GATE IC 7402 1
6 EXOR GATE IC 7486 1
7 DIGITAL POWR SUPPLY (0-5)V 1
8 DIGITAL TRAINER (0-12)V 1

THEORY:
Boolean theorems are used for minimizing the Boolean function with will help in
minimizing the number of Logic gates.

DEMORGAN’S THEOREM:

1. (A.B)’=A’+B’
2. (A+B)’ = A’.B’

BOOLEAN FUNCTIONS:

1. F=X+XY
2. F=(AB’C’+AB’C+ABC+ABC’)(A+B)
3. F= (A’+B’)’

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SIMPLIFICATION:

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SIMPLIFICATION:

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PROCEDURE:

1. Write the truth table for the above given functions.

2. Implement the function using basic Gate.
3. Verify the truth table.

QUESTIONS:
1. Define Boolean algebra
2. State the Boolean theorems
3. What do you mean by universal gate?
4. State the Duality theorem
5. Draw the timing diagram for the following function (((A+B).C)’).D
6. Write truth table for 2 I/P OR, NOR, AND and NAND gate?
7. Implement all logic gates by using Universal gate?
8. Why NAND and NOR gates are called Universal Gates?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the Boolean functions are implemented using basic gates and verified.

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EX No: 3 DESIGN AND IMPLEMENTATION OF ADDERS / SUBTRACTORS

DATE:
AIM:
To design and verify the operations of Half adder, Full adder, Half subtractor and Full subtractor
using Logic gates.
APPARATUS REQUIRED:
SPECIFICATIO
Sl.No. COMPONENTS Qty
N/RANGE
1 OR GATE IC7432 1
2 EXOR GATE IC7486 1
3 AND GATE IC 7408 1
4 NOT GATE IC 7404 1
5 Digital Trainer Kit (0 – 12) V 1
6 Digital Power Supply (0 – 5) V 1

HALF ADDER
THEORY:
A basic module used in binary arithmetic elements is the half adder. The function of half adder is
adding two binary digits producing a sum and carry. These are two inputs to the half adder
designated sum and carry .The half adder performs binary addition operation for two binary inputs.
This is Arithmetic addition, not logical and Boolean addition.
If either of the inputs is a ‘1’ but not both, the output on the Sum will be ‘1’.
If both the inputs are 1’s then the output on the C will be 1 .for other states, there will be a ‘0’
output on the carry line. The relationship can be written as
Sum = AB
Carry = A.B

CIRCUIT DIAGRAM: TRUTH TABLE

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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FULL ADDER:
THEORY:
A full adder is the combinational circuit that forms the arithmetic sum of three input bits. The full
adder accepts three inputs and generates a sum output and carries output. The relationship can be
written as
Sum = (A  B)  C
Carry = AB + (A  B) C
The full Adder can be constructed using two Half Adders and an AND Gate
CIRCUIT DIAGRAM: TRUTH TABLE:

A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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HALF SUBTRACTOR:
THEORY:
A Half Subtractor is a combinational circuit that subtracts two bits and produces their difference
.It also has an output to specify if a 1 has been borrowed. Designate the minuend bit by X and the
subtrahend bit by Y. To perform X - Y, we have to check the relative magnitude of X and Y. The
result is called difference bit .The half subtractor needs two outputs .One output generates the
difference and will be designated by the symbol D. The second output, designated B for borrow,
generates the binary signal that informs the next stage that a 1 has been borrowed

CIRCUIT DIAGRAM: TRUTH TABLE

A B D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

FULL SUBTRACTOR
THEORY
A full subtractor is a combinational circuit that performs the subtraction between two bits, taking
into account that 1 has been borrowed by a lower significant stage. The circuit has three inputs and
two outputs .The three inputs X, Y, Z denotes the minuend, subtrahend and previous borrow
respectively .The two outputs D and B represents the difference and output borrow respectively

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CIRCUIT DIAGRAM:

TRUTH TABLE:

Input Output
x y z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
1. Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Check for the output as given in the characteristics table by the glowing of LED.

QUESTIONS:

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1. Draw circuit diagram of Half Adder circuit?

2. Draw circuit diagram of Full Adder circuit?
3. Draw Full Adder circuit by using Half Adder circuit with minimum no. of logic gate?
4. Write Boolean function for half adder?
5. Write Boolean function for Full adder?
6. Design the half Adder & Full Adder using NAND-NAND Logic.
7. Draw circuit diagram of Half Subtractor circuit?
8. Draw circuit diagram of Full Subtractor circuit?
9. Draw Full Subtractor circuit by using Half Subtractor circuit with minimum no. of logic
gate?
10. Write Boolean function for half Subtractor?
11. Write Boolean function for Full Subtractor?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the Half Adder, Full Adder, Half Subtractor and Full Subtractor circuits are designed and
constructed using Logic gates and the truth tables are verified.

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EX No: 4 DESIGN OF CODE CONVERTERS

Date:

AIM:

To design and verify the operations of Binary to Gray code converter, Gray to Binary code
converter, BCD to Excess 3 code converter and Excess 3 to BCD code converter using Logic gates.

APPARATUS REQUIRED:

SPECIFICATIO
Sl.No. COMPONENTS Qty
N/RANGE
1 OR GATE IC7432 1
2 3 INPUT AND GATE IC7411 1
3 EXOR GATE IC7486 1
4 NOT GATE IC7404 1
5 AND GATE IC7408 1
6 Digital Trainer Kit (0 – 12) V 1
7 Digital Power Supply (0 – 5) V 1

THEORY:
The communication systems requires various types of data codes for security purposes, so we need
some code converters to convert the actual data into some other form. The commonly used code
converters are binary code to gray code and BCD to Excess 3 code and vice versa converters.

Binary code to Gray code converter:

Gray code is a one bit change code which is used in many decoding applications like Optical shaft
encoders. This circuit accepts a 4 bit binary code input and converts into its equivalent 4 bit gray
code.

BCD code to Excess-3 code converter:

Excess – 3 code means adding the binary value 011(i.e., 3d) to the original data. BCD stands for
Binary Coded Decimal, it is a number system rages from the decimal values 0 and 9. This circuit
accepts the 4 bit BCD value and converts into its equivalent 4 bit Excess-3 code.

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CIRCUIT DIAGRAM:
1. BINARY TO GRAY CODE CONVERTER:
b0 g0

1
3 g1
b1 2 7486

4
6
b2 5 7486 g2

9
8 g3
b3 10 7486

TRUTH TABLE:

Input Binary Code Output Gray Code

B0 B1 B2 B3 G0 G1 G2 G3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

2. GRAY TO BINARY CODE CONVERTER:

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g0 b0

1
3 b1
g1 2 7486

4
7486 6 b2
g2 5

9
7486 8 b3
g3 10

TRUTH TABLE:

Input Gray Code Output Binary Code

G0 G1 G2 G3 B0 B1 B2 B3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

3. BCD TO EXCESS-3 CODE CONVERTER:

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TRUTH TABLE:

EXCESS-3 TO BCD CODE CONVERTER:

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TRUTH TABLE:

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PROCEDURE:
1. Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Check for the output as given in the characteristics table by the glowing of LED.

QUESTIONS:
1. What is Excess-3 code? Why it is called Excess-3 code?
2. What is the application of Excess-3 Code?
3. What is ASCII code?
4. Whether Excess-3 code is weighted or unweighted?
5. Out of the possible 16 code combination, how many numbers used in Excess-3 code?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the Binary to Gray code converter, Gray to Binary code converter, BCD to Excess 3
code converter and Excess 3 to BCD code converter circuits are designed and constructed using
Logic gates and their truth tables are verified

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Ex. No: 5 DESIGN OF MULTIPLEXER/DE-MULTIPLEXER

DATE:

AIM:

To design and construct a combinational circuit for Multiplexer and De-Multiplexer using Logic
gates
APPARATUS REQUIRED:
SPECIFICATIO
Sl.No. COMPONENTS Qty
N/RANGE
1 OR GATE IC7432 1
2 3 INPUT AND GATE IC7411 2
3 2 INPUT AND GATE IC7408 1
4 NOT GATE IC7404 1
5 Digital Trainer Kit (0 – 12) V 1
6 Digital Power Supply (0 – 5) V 1

MULTIPLEXER:
THEORY:

• Multiplexing means transmitting a large number of information units over a smaller number
of channels or lines
• A Digital Multiplexer is a combinational circuit that selects binary information from one of the
many input lines and directs it to a single output line
• The selection of a particular input line is controlled by a set of selection lines
• Normally there are 2 n input lines and n selection lines whose bit combinations determine which
input is selected
• A 4-to-1-line Multiplexer is shown in the fig. Each of the four input lines I 0 to I3 is applied to
one input of an AND gate Selection lines S 1 and S0 are decoded to select a particular AND
Gate
• Consider the case S1 S0=10 .the AND Gate associated with input I2 has two of its inputs
equal to 1 and third input connected to I2 he other three AND Gates have at least one input
equal to 0, which makes their outputs equal to 0 The OR Gate output is now equal to the value
of I2, thus providing a path from the selected input to to the output
• A Multiplexer is also called Data Selector, since it selects one of many inputs and steers the
binary information to the output line

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CIRCUIT DIAGRAM:

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TRUTH TABLE:

Data Input Select Line

Output
( X- Don’t care)
(0,1) S1 S0
I0=X(0,1) 0 0 I0=X(0,1)
I1=X(0,1) 0 1 I1=X(0,1)
I2=X(0,1) 1 0 I2=X(0,1)
I3=X(0,1) 1 1 I3=X(0,1)

DEMULTIPLEXER:
THEORY
• A Demultiplexer is a circuit that receives information on a single line and transmits this
information on one of 2 n possible output line
• A decoder with an Enable input can function as a Demultiplexer
• The selection of a specific output line is controlled by a bit value of n selection lines.
• The Decoder can function as a Demultiplexer if I line is taken as a data input line and lines S1
and S0 are taken as a selection lines.
• The single input variable I have a path to all 4 outputs, but the input information is directed to
only one of the output lines, as specified by the binary values of the two-selection linesS1 and
S0.

CIRCUIT DIAGRAM:

TRUTH TABLE

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Data Input (I) Select Line

Output
( X- Don’t care) S1 S0
(0,1)
X(0,1) 0 0 D0=X(0,1)
X(0,1) 0 1 D1=X(0,1)
X(0,1) 1 0 D2=X(0,1)
X(0,1) 1 1 D3=X(0,1)

QUESTIONS:
1. Realise 3 inputs AND gate and 3 input OR gate using 4x1 MUX and 2 input AND function
using 2x1 MUX.
2. Realise a simple Boolean function using 4x1 MUX.
3. What is Multiplexing?
4. What is the difference between Multiplexing and Demultiplexing?
5. What are different types of Multiplexing techniques?
6. What is a Demultiplexer?
7. What are the difference between Demultiplexer and Decoder?
8. How many select lines are needed to construct a 1x8 Demultiplexer? Design it.
9. What are the advantages and disadvantages of Multiplexer?
10. What is the application of Demultiplexer?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

CONCLUSION:
Thus the Multiplexer, Demultiplexer are designed and constructed using logic gates.

EX.NO: 6 DESIGN OF ENCODER / DECODER

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DATE:

AIM:

To design and construct a combinational circuit for Encoder and Decoder using Logic gates.

APPARATUS REQUIRED:
SPECIFICATION
Sl.No. COMPONENTS Qty
/RANGE
1 OR GATE IC7432 1
2 3 INPUT AND GATE IC7411 2
3 2 INPUT AND GATE IC7408 1
4 NOT GATE IC7404 1
5 Digital Trainer Kit (0 – 12) V 1
6 Digital Power Supply (0 – 5) V 1

ENCODER:
THEORY
• An Encoder is a digital circuit that performs the inverse operation of a decoder
• An Encoder has 2n input lines and n output lines .The output lines generates the binary code
corresponding to the input value
• The above circuit shows the operation of Priority Encoder .The priority Encoder is an Encoder
Circuit that includes the priority function.
• The operation of the priority encoder is such that if two or more inputs are equal to one at the
same time, the input have the highest priority will take precedence
• In the truth table, the X ‘s are don’t care conditions that designate the fact that binary value
may be equal to 1 or 0
• Input D3 has the highest priority level; so regardless of the value of other inputs, when this
input is 1,the output of xy is 11 (binary 3). D2 has the next priority level .The output is 10
(binary 2) if D2 is equal to 1, provided D3=0, regardless of the value of other two lower priority
inputs .the output o for D1 is generated only if higher priority inputs are 0 and so on down the
priority level. A valid output indicator, designated by Z is set to 1 only when one or more of
the inputs are equal to 1 .If all the inputs are 0,Z is equal to 0, and the other two outputs of the
circuits are not used

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CIRCUIT DIAGRAM:

D0

X = D2 + D3
Y = D1D2’ + D3
Z = D0 + D1+ D2 + D3

TRUTH TABLE:

D0 D1 D2 D3 X Y Z
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

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DECODER
THEORY
• Discrete quantities of information are represented in digital systems with binary codes. A
decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n output lines
• The decoder presented here is called 2 to 4 line decoder .The two inputs are decoded into 4
outputs, each output representing one of the minterms of the 2 input variables. The 2 inverters
provide complement of the inputs, and each of the 4 AND gates generate one of the minterms.
CIRCUIT DIAGRAM

D0 = A’B’
D1 = A’B
D2 = AB’
D3 = AB

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TRUTH TABLE:
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

PROCEDURE:
1. Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Verification of glowing LED confirms the required data in the truth table.

QUESTIONS:

1. What is an Encoder?
2. Design a four-bit Priority Encoder.
3. What is a Decoder?
4. Difference between Decoder and Demultiplexer.
5. Design a BCD to Gray code converter using BCD to Decimal Decoder and NAND
gates.
6. What is a decoder and obtain the relation between the number of inputs ‘n’ and outputs
7. What is decoder?
8. What do you mean by encoder?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

CONCLUSION:
Thus the Encoder and Decoder are designed and constructed using logic gates.

Ex. No: 7 DESIGN OF 4 BIT ADDERS / SUBTRACTORS

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DATE:

AIM:

To design and verify the operations of 4 bit binary adder, 4 bit binary Subtractor using IC 7483

APPARATUS REQUIRED:

SPECIFICATION/
S.No. COMPONENTS Qty
RANGE
1 4 BIT BINARY ADDER IC7483A 1
2 EXOR, 3 Input AND, NAND GATE IC7486, IC7410, IC7400 1
3 Digital Trainer Kit (0 – 12) V 1
4 Digital Power Supply (0 – 5) V 1

THEORY:
The 7483A high speed 4 bit binary full adders with internal carry look ahead accept two 4 bit
binary words A0 – A3 & B0 – B3 and a carry input, C0. They generate the binary sum outputs, S0
– S3 and a carry output, C4.

The circuit adds the two 4 bit binary words (A and B) plus the incoming carry. the binary sum
appears on the sum outputs (S0 – S3) and outgoing carry (C4) output.
C0 + (A0 + B0) + 2(A1 + B1) + 4(A2 + B2) + 8(A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4

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CIRCUIT DIAGRAM:
4 BIT ADDER:

TRUTH TABLE:

4 BIT ADDER / SUBTRACTOR:

4 BIT ADDER/SUBTRACTOR

1
3 10 9 y0
b0 2 7486 8 A1 S1 6 y1
3 A2 S2 2 y2
1 A3 S3 15 y3
4 A4 S4
6 11 14 cout
b1 5 7486 7 B1 CY O
4 B2
16 B3
9 B4 7483A
8 13
b2 10 7486 CY I

12
11
b3 13 7486

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TRUTH TABLE:

Input Output

A B Mode Sum Carry

A3 A2 A1 A0 B3 B2 B1 B0 M S3 S2 S1 S0 Cout
0 0 0 1 0 1 1 1 0 1 0 0 0 0
1 0 0 1 0 1 1 1 (Add) 0 0 0 0 1
1 0 0 1 0 1 1 1 1 0 0 1 0 0
1 0 0 1 1 0 1 0 (Sub) 1 1 1 1 0

PIN DIAGRAM: IC 7483A

IC 7483A

LOGICAL SYMBOL:

PROCEDURE:
1. Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Check for the output as given in the characteristics table by the glowing of LED.

QUESTIONS:
1. What are the difference between Boolean addition and binary addition?
2. How can an adder circuit be used as subtractor?
3. What is a carry look ahead adder?
4. How will you implement a comparator using the adder/subtractor circuit?
5. What are the difference between a parallel adder and serial adder?
6. Give some applications of parallel adder.

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

CONCLUSION:
Thus the operation of IC7483A - 4 bit binary adder was studied and a 4 bit binary adder /
Subtractor was designed using IC 7483A.

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Ex. No:8 DESIGN OF PARITY CHECKER / GENERATOR

DATE:

AIM:

To design and verify the operation of 16 bit odd / even parity checker generator using IC74180

APPARATUS REQUIRED:
SPECIFICATION
Sl.No. COMPONENTS Qty
/RANGE
1 8 bit odd/parity checker IC74180 2
2 Digital Trainer Kit (0 – 12) V 1
3 Digital Power Supply (0 – 5) V 1

THEORY:
16 BIT ODD/EVEN PARITY CHECKER GENERATOR:
IC74180 is a monolithic, 8 bit parity checker / generator which features control inputs and
even/odd outputs to enhance operation in either odd or even parity applications. Cascading these
circuits allows unlimited word length expansion. Typical application would be to generate and
check parity on data being transmitted from one register to another.16 bit circuit can be designed
by cascading two IC74180.
TRUTH TABLE: PIN DESCRIPTION:

DESCRIPTION

L – Logic low H – Logic High X – Don’t care

CIRCUIT DIAGRAM:

I8 8 5 I0 8 5 LOGIC 1
D0 EVEN D0 EVEN
I9 9 6 I1
9 6 ON
D1 ODD 10 D1 ODD
10 EVEN PARITY
I10 D2 I2 11 D2
11
I11 D3 I3 12 D3
I12 12 I4
D4 13 D4
I13 13 I5
D5 1 D5
I14 1 I6
D6 2 D6
2
I15 D7 I7 D7
lOGIC 1 3 3
PE 4 PE
4
PO 74180-1 PO 74180-2
lOGIC 0

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PIN DIAGRAM: LOGICAL SYMBOL:

PROCEDURE:
1. Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Check for the output as given in the characteristics table by the glowing of LED.

QUESTIONS:
1. What is meant by parity?
2. What is meant by error detecting code?
3. What is the use of parity generator and parity checker?
4. What is meant by hamming code?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the 16 bit odd / even parity checker generator was designed and verified using IC74180, 8
bit odd / even parity checker generator.

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Ex. No: 9 DESIGN OF MAGNITUDE COMPARATOR

DATE:

AIM:

To design and verify the operation of 2 bit magnitude comparator using logic gates and study of 4
bit magnitude comparator using IC7485

APPARATUS REQUIRED:
SPECIFICATIO
S.No. COMPONENTS Qty
N/RANGE
1 3 INPUT OR GATE IC7411 2
2 EXOR IC7486 1
3 OR GATE IC7432 2
4 NOT GATE IC7404 2
5 Digital Trainer Kit (0 – 12) V 1
6 Digital Power Supply (0 – 5) V 1

THEORY:
2 BIT MAGNITUDE COMPARATOR:
A comparator is a special combinational circuit designed primarily to compare the relative
magnitude of two binary numbers. It results as A>B, A<B and A=B values.

4 BIT MAGNITUDE COMPARATOR USING IC7485:

IC7485 is a high speed, expandable 4-bit magnitude comparator which compares two 4-bit words
in any monotonic code (binary or BCD or other) and generates three outputs: A less than B, A
greater than B and A equal to B.

PROCEDURE:
1.Connect the components as per the given circuit.
2. Apply the bits as per the truth table.
3. Check for the output as given in the characteristics table by the glowing of LED.

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CIRCUIT DIAGRAM:
2 BIT MAGNITUDE COMPARATOR:

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TRUTH TABLE:
Input Output
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

QUESTIONS:
1. What is a Comparator?
2. What are the applications of Comparator?
3. Which logic is used as 1 bit comparator?
4. Derive the Boolean expressions of one bit comparator and two bit comparators.
5. How do you realize a higher magnitude comparator using lower bit comparator
6. Design a 2 bit comparator using a single Logic gates?
7. Design an 8 bit comparator using a two numbers of IC 7485?

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the 2 bit magnitude comparator was constructed using logic gates and an 4 bit
magnitude comparator using IC7485 was studied

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Ex. No:10 DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

DATE:

AIM:
To construct the following Shift Registers
i.)Serial in Serial out Shift left Register
ii)Serial in Serial out Shift Right Register
iii)Serial in Parallel out
iv)Parallel in Serial out
v)Parallel in Parallel out Shift register

APPARATUS REQUIRED:

SPECIFICATION
Sl.No. COMPONENTS Qty
/RANGE
1 D FLIP-FLOP IC7474 2
2 Digital Trainer Kit (0 – 12) V 1
3 Digital Power Supply (0 – 5) V 1

SERIAL-IN SERIAL OUT

THEORY
Shift Register is very important in applications involving the storage and transfer of data
in Digital Systems. The basic difference between a register and counter is that a register has no
specified sequence of states. A register, in general is used for temporary storing and shifting data
in Digital systems.
This type of Shift Register enters data serially that is, one bit at a time on a single line .It
produces the stored information on its output also in serial form.

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CIRCUIT DIAGRAM - SERIAL IN SERIAL OUT SHIFT RIGHT REGISTER

TRUTH TABLE

CLK D0 D1 D2 D3
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
QA QA QB QB QC QC QD QD
D IN 2 5 12 9 2 12 9 D OUT
FF2
> 3 > 11 >3 >11
FF2 FF1 FF2 FF1

CP

SERIAL-IN PARALLEL OUT

THEORY
This type of Shift Register enters data serially that is, one bit at a time on a single line.
Once the data are stored, each bit appears on its respective output line and all the bits are appeared
simultaneously, rather than on a bit-by bit basis as with the serial output.
CIRCUIT DIAGRAM

D0 D1 D2 D3

SERIAL IN
D 2 5 12 9 2 5 12 9

FF2
> 3 > 11 >3 >11
FF2 FF1 FF2 FF1

CP

TRUTH TABLE

CLK INPUT D0 D1 D2 D3
1 1 1 0 0 0
2 1 1 1 0 0
3 1 1 1 1 0
4 1 1 1 1 1

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PARALLEL IN PARALLEL OUT REGISTERS

THEORY
The Parallel in Parallel out register employs both the methods : Immediately following the
simultaneous entry of all data bits ,the bits appear on the parallel outputs

CIRCUIT DIAGRAM
B C D
A

QA QA QB QB QC QC QD QD
D IN 2 5 12 9 2 5 12 9
FF2
> 3 > 11 >3 >11
FF2 FF1 FF2 FF1

CP

QA
QB QC QD

TRUTH TABLE
CLK A B C D QA QB QC QD
1 000 1 0 0 0 1
2 0011 0 0 1 1
3 0111 0 1 1 1
4 1111 1 1 1 1

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PROCEDURE:
1. The components are connected as shown in the circuit diagram.
2. The clock pulse is given and it is checked whether the bits shifts.

QUESTIONS:
1. Can we implement the Shift registers using flip flops other than D flips flop.
2. Differentiate counter and register?
3. What is a buffer?
4. What is the operation of D flip-flop?
5. Define shift register counter.

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the i) Serial in Serial out Shift left Register ii) Serial in Serial out Shift Right Register
iii) Parallel in Parallel out Shift register iv) Serial in Parallel out v) Parallel in Serial out are
verified using truth table and its truth table is verified.

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Ex. No: 11 DESIGN AND IMPLEMENTATION OF SYNCHRONOUS AND

DATE: ASYNCHRONOUS– COUNTERS

AIM:
To design and construct the following asynchronous and synchronous counter and
to verify its truth table.

APPARATUS REQUIRED:

SPECIFICATIO
S.No. COMPONENTS Qty
N/RANGE
1 JK FLIP-FLOP IC7476 2
2 AND GATE IC7408 1
3 OR GATE IC7432 1
4 Digital Trainer Kit (0 – 12) V 1
5 Digital Power Supply (0 – 5) V 1

3 BIT RIPPLE COUNTER

THEORY
Three JK flip-flops are used with their inputs connected to Vcc. Negative Edge Triggering
is used. The small circle in the CP input indicates that the flip-flop complements during a Negative
going transition or when the output to which is connected goes from 1 to 0 .The flip-flop changes
one at a time propagates through the counter in a ripple fashion .Ripple counter are called as
Asynchronous Counter

TRUTH TABLE

CLK Q3 Q2 Q1
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

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3 BIT SYNCHRONOUS COUNTER

THEORY
When a Counter is Clocked such that each Flip flop in the Counter is Triggered at the
same time ,the counter is called Synchronous counter
QA changes on each clock pulse as we progress from its original state to its final stack and
then back to its original state .In Synchronous binary counter, the flip-flop in the lowest –order
position is complemented with every pulse A flip-flop in any other position is complemented with
a pulse provided all the bits in the lower order positions are equal to 1 . the binary count indicates
that next higher order bit be complemented .Synchronous binary counters have a regular pattern
and can be easily constructed with complementing flip-flops and gates .The counter could also be
triggered on the positive edge of the pulse

TRUTH TABLE:

CLK Q3 Q2 Q1
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

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CIRCUIT DIAGRAM:

Q2
Q1 Q3

HIGH
1 3 PRESET
+5V
2
J1 2 J2 7 2
15 9 J1
4 11 15
4
FF2 FF3
> FF1 >6 >
1 1

K1 K2
16 12 K1
3 8 16
3

CP CLEAR
+5V

PROCEDURE:
1. The components are connected as shown in the circuit diagram.
2. The counter is set initially in the reset position.
3. Apply the clock pulse. It starts counting.
4. Continue giving the clock pulse and check for the output as given in the truth table.
5. The output is indicated by the LED display. The glowing of LED’s confirming to required data
in the truth table is verified.

QUESTIONS:
1. What is an asynchronous counter?
2. How is it different from a synchronous counter?
3. Realize asynchronous counter using T flip-flop
4. What are synchronous counters?
5. What are the advantages of synchronous counters?
6. What is an excitation table?
7. Write the excitation table for D, T FF
8. Design mod-5 synchronous counter using T FF.

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus 2 Bit ripples counter, 3 Bit ripple Counter, BCD Ripple Counter is constructed using JK
flip-flop and truth table is verified.

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EX.NO:12 CODING COMBINATIONAL CIRCUITS USING HARDWARE

DATE: DESCRIPTION LANGUAGE

AIM:

To write the verilog coding for various combinational circuits.

SOFTWARE REQUIRED:
Model sim

CODING:

AND GATE XOR GATE HALF ADDER

module and1(a,b,y); module xorg(x,y,z); module HA(x,y,s,c);
input a,b; input x,y; input x,y;
output y; output z; output s,c;
and(y,a,b); xor(z,x,y); xor(s,x,y);
endmodule endmodule and(c,x,y);
endmodule
MAGNITUDE COMPARATOR MULTIPLEXER
module mag(a,b,out); module muxe(i,out,sel,rst);
input[1:0]a; input [3:0]i;
input [1:0]b; input [1:0]sel;
output [2:0]out; input rst;
reg [2:0]out; output out;
always @ (a or b) reg out;
out=(a==b?3'b100:a<b?3'b010:3'b001); always@(i or rst)
endmodule if(rst==0)
begin
FULL ADDER case(sel)
module FA(a,b,c,s,cy); 2'b00 : out<=i[0]; 2'b01 :
input a,b,c; out<=i[1]; 2'b10 : out<=i[2]; 2'b11
output s,cy; : out<=i[3]; 2'bxx : out<=1'bx;
wire c1,c2,c3; endcase
xor(s,a,b,c); end
and(c1,a,b); else
and(c2,b,c); out<=1'b0;
and(c3,a,c); endmodule
or(cy,c1,c2,c3);
endmodule

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QUESTIONS:
1. Define HDL?
2. Describe the term concurrent and sequential.
3. List the different types of modelling.
4. List the various HDL tools.
5. With an example explain and implement the logic circuit with all modelling.

MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the verilog coding for various combinational circuits output is verified

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Ex.No:13 CODING SEQUENTIAL CIRCUITS USING HARDWARE DESCRIPTION

DATE: LANGUAGE

AIM:

To write the verilog coding for various Sequential circuits

SOFTWARE REQUIRED:
Model sim
CODING:
D FLIP FLOP
module d_ff(d,q,clk,rst);
input d, clk, rst;
ouput q;
reg q;
always @ (posedge clk or posedge rst)
if (rst == 1)
q = 1’b0;
else
q = d;
endmodule
JK FLIP FLOP
module jk_ff(j,k,q,clk,rst);
input j,k,clk,rst;
output q;
reg q;
always @ (posedge clk or posedge rst)
if (rst == 1)
q = 1’b0;
else
q = ((j & (~q)) | ((~k) & q));
endmodule
T FLIP FLOP
module t_ff(t,q,clk,rst);
input t,clk,rst;
output q;
reg q;
always @ (posedge clk or posedge rst)
if (rst == 1)
q = 1’b0;
else
q = ((t & (~q)) | ((~t) & q));
endmodule

RS FLIP FLOP

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module sr_ff(s,r,q,clk,rst);
input s,r,clk,rst;
output q;
reg q;
always @ (posedge clk or posedge rst)
if (rst == 1)
q = 1’b0;
else
q = (s | ((~r) & q));
endmodule

SEQUENTIAL CIRCUIT

D FLIP FLOP

JK FLIP FLOP

T FLIP FLOP

RS FLIP FLOP

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MARK ALLOCATION
Experimental Setup 10
Output & Result 5
Viva 5

RESULT:
Thus the verilog coding for various sequential circuits output is verified.

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