Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
8 views13 pages

CMOS Inverter Design Analysis

The document discusses the design and operation of an inverter logic gate. It describes the transistor-level implementation using an NMOS and PMOS transistor. Graphs show propagation delay, voltage over time, and voltage switching thresholds. Changing transistor widths, thresholds, technology nodes, and fanout alter the electrical characteristics.

Uploaded by

Sunny Rao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
8 views13 pages

CMOS Inverter Design Analysis

The document discusses the design and operation of an inverter logic gate. It describes the transistor-level implementation using an NMOS and PMOS transistor. Graphs show propagation delay, voltage over time, and voltage switching thresholds. Changing transistor widths, thresholds, technology nodes, and fanout alter the electrical characteristics.

Uploaded by

Sunny Rao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 13

Q1

Inverter:
The basic logic gate inverter involves two complementary transistors, an NMOS (n-type metal-
oxide-semiconductor) transistor and a PMOS (p-type metal-oxide-semiconductor) transistor.
Vin Vout
0V Vdd
Vdd 0V

Schematic:
Ratio effect for an inverter depends upon length and width of transistor.
Wp
/W n
Lp
β=
Ln

β=1.67 for inverter shown in below figure

Verilog:
Layout & 3D:

Voltage vs Time (90nm):


Propagation delays, specifically tPHL (propagation delay from a high to low logic level) and tPLH
(propagation delay from a low to high logic level), in this inverter both are match which is 5ps
provide optimal performance as shown in below figure.

Average Propagation Delay


t PLH +t PHL
t p=
2
Voltage and Current:

Log Scale:
Resistance:
Higher channel resistances can lead to slower switching speeds and
longer propagation delays, as they increase the time it takes for the
transistors to fully switch on or off.
t n=Rn C out

t p=R p C out

Rn =1/ βn [V dd −V tn ]

R p =1/ β p [V dd −V tp ]

Total resistance at output 254𝝮 and Rise delay and Fall delay show
given in figure of navigator
Voltage vs Voltage:
The threshold voltage of each transistor affects its turn-on behavior. In an inverter, the threshold
voltages of the NMOS and PMOS transistors determine the input voltage levels required to
switch between logic states. Which is 50% of Vdd for Vth=0.560 V, while gate Voltage Vg varies
from 0 to 1.2 V. Higher threshold voltages typically result in slower switching speeds and longer
propagation delays, as they require higher input voltages to overcome the threshold

If inverter design on base of width of PMOS equal to width of NMOS, Resistance get Varied to
279 ohm
Threshold Voltage reduces to 0.476

Voltage vs Time:
Q2
Size Changing(90nm):
If Wn=Wp=3Lg
Voltage vs Time:

Threshold Voltage:
Smaller Foundry(45nm):

Voltage vs Current:
Noise Margin:
N M H =|V OHmin−V I Hmin|

N M L =|V ILm ax −V OL m ax|

Q3
(90nm Process) Fanout 5x:
We add 9.45fF capacitance in initial capacitance 1.80fF at output as given in Q1, to
make five time greater of input capacitance 2.25fF at gate of inverter.
Voltage vs Time
We observed there increase propagation delay increase to 21ps as show in figure by adding
capacitance at load, power consumptions also increase to 16.597uW, Idd maximum goes to
0.346mA. Rise delay goes from 0.014 ns to 0.89 ns, Fall delay from 0.008 ns to 0.049 ns.
Voltage vs Voltage:

Technology(45nm)
Transient of Inverter:
Voltage vs Voltage:

You might also like