* The different ways that a processor can access data are referred to as addressing modes. © The addressing modes of any processor can be broadly classified as : = Data addressing modes. Data Addressing Modes ‘The data addressing modes can be further classified as 1. Addressing modes for accessing immediate and register data (register and immediate modes). 2. Addressing modes for accessing data in memory (memory modes). 3. Addressing modes for accessing I/O ports (I/O modes). Addressing Modes for Accessing Immediate and Register Data 1. Register addressing mode : This mode specifies the source operand, destination operand, or both to be contained in an 8086 register. Direction of data flow MOV AL, BL BL Destination register ‘Source register ‘Note : Both source and destination operands are in 8086 ragister Examples : MOV BX, CX ; Copies the 16-bit contents of CX into BX MOV CL, BL ; Copies 8-bit contents of BL into CL. 2. Immediate addressing mode : + In an immediate mode, 8 or 16-bit data can be specified as a part of instruction, Examples : MOV BL, 26H ; Copies the 8-bit data 26H into BL. MOV CX, 4567H _; Copies the 16-bit data 4567H into CX, TECHNICAL PUBLICATIONS”. An up thrust for knowledgeMOV AL, 20H [= }-——» Destination operand Immediate data is a 8086 register 25 a Source operand 15 9 pee [a Destination operand Immediate data is a 6086 register as a source operand Note : Arrow indicates direction of data flow Addressing Modes for Accessing Data in Memory * As mentioned before, the Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However, the EU cannot directly access the memory operands. It must use the BIU segment registers to access memory operands. For example, when the EU needs to access a memory location, it sends an offset value to the BIU. This offset is also called the Effective Address (EA). Note that EA is displacement of the desired location from the segment base. * As mentioned before, the BIU generates a 20-bit physical address after shifting the contents of the desired segment register four bits to the left and then adding the 16-bit BA to it. * There are six ways to specify Effective Address (EA) in the instruction. a. Direct addressing mode b. Register indirect addressing mode ¢. Based addressing mode d. Indexed addressing mode e. Based indexed addressing mode £. String addressing mode. 1. Direct addressing mode : + In this mode, the 16-bit Effective Address (EA) is taken directly from the displacement field of the instruction. * The displacement (unsigned 16-bit or sign-extended 8-bit number) is stored in the location following the instruction opcode. TECHNICAL PUBLICATIONS”. An up thruat-for knowtodgeMicroprocessors: 1-28 (8086 Processor Example : Memory AL 408 | 430014 MOV AL, [3000H] 60H }+————_|_ 60H | 13000H=— 10000H + 3000H os [ab astro so0 Memory MOV [3000H], CX Rey 10000 H + 3000 H Pe (7 DSx(10 H) + 3000 H Note; 1, Assume DS = 1000 Physical address = OS x (10H) + 3000H= 1000[0] + 3000H = 13000H 2, Arrow indicates direction of data flow. MOV CL, [9823H] ; This instruction will copy the contents of the ; memory location, at a displacement of 9823H from the ; data segment base, into the CL register. Here, 9823H is ; the Effective Address (EA) which is written ; directly in the instruction. 2. Register indirect addressing mode : « In this mode, the EA is specified in either a pointer register or an index register. © The pointer register can be either base register BX or base pointer register BP and index register can be either Source Index (SI) register or Destination Index (DI) register. * The 20-bit physical address is computed using DS and EA. Example : 1, MOV [DI], BX ; The instruction copies the 16-bit contents of BX into a ; memory location offset by the value of EA specified in DI ; from the current contents in DS. Now, if [DS] = 7205H, ; [DI] =0030H, and [BX] = 8765H, then after MOV [DI], BX, ; content of BX (8765H) is copied to memory locations 3 72080H. and 72081H. TECHNICAL PUBLICATIONS” An up thrust far knowlockgeMOV BX, [CX] . DS x (10H) Physical address 2000H Effective address ex 2. MOV DL, [BP] ; This instruction copies the 8-bit ; contents in DL from the memory location offset by the ; value of BA specified in BP from the contents of SS. ; Because data addressed by BP are by default located in ; Stack Segment (5S). 3. Base-Plus-Index-addressing : Base-plus-index addressing is similar to indirect addressing because it indirectly addresses memory data. e This addressing uses one base register (BP or BX), and one index register (DI or SI) to indirectly address memory. « The base register often holds the beginning location of a memory array, while the index register holds the relative position of an element in the array. Remember that whenever BP addresses the memory data, the contents of stack segment, BP and index register are used to generate physical address. Locating data with base-plus-index addressing : See Fig. 1.7.1 on next page ‘Locating array data using base-plus-index addressing = ‘A main use of the base-plus-index addressing mode is to address elements in a memory array. Suppose that the array is located in the deta segment beginning from memory location ARRAY. To access a particular element within the array we have to load the BX register (base) with the beginning address of the array, and the DI register (index) with the element number to be accessed. This is illustrated in Fig. 1.7.2. TECHNICAL PUBLICATIONS"- An up thrust for rowecigeMOV CX, [BX+D]] Fig. 1.7.2 TECHNICAL PUBLICATIONS". An up thrust for knoutectewyKY” Microprocessors 1-31 8086 Processor 4, Register relative addressing : « Register relative addressing is similar to base-plus-index addressing, Here, the data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP, BX, DI or SI). © Remember that displacement should be added to the register within the [ ]. This is illustrated in the Fig, 1.7.3. © Displacement can be any 8-bit or 16-bit number. MOV CX, [BX + 0003H] or MOV CX, [BX + 3] DS x (10 H) 41000H Displacement 3H Fig. 4.7.3 Deplacernent/ “MOV AL, OFF_ADD | (pr + 4}. Example: MOV AL, LAST {SI + 2] ; This instruction copies the contents of the 20-bit address computed from the displacement LAST, SI + 2 and DS into AL. Addressing array data with register relative : The Fig. 1.7.4 shows how to address data element within the array with register relative addressing. TECHNIGAL PUBLICATIONS”. An up thrust for knowledge‘Microprocessors 1-32 8086 Processor MOV GX, ARRAY [DI] Displacement in the segment register Fig. 1.7.4 5. Base relative plus index addressing = © The base relative plus index addressing mode is similar to the base plus index addressing mode, but it adds a displacement, besides using a base register and an index register to generate a physical address of the memory. * This addressing mode is suitable to address data within MOV ALJBX + SI + 10H] the two dimensional array. Addressing data with base relative AL plus index : The Fig. 1.7.5 shows how data can be accessed with base relative plus index addressing mode. Addressing arrays with base ,, relative-plus-index : = This addressing mode is useful in addressing two dimensional 5! array, Two dimensional array usually stores records. ps DS x (10H) Fig. 1.7.5 TECHNICAL PUBLICATIONS”. An up thrist for knowedgegr Microprocessors 1-33 8086 Processor . For example, student record such as its name, roll no. etc. Therefore, each record. contains number of data elements. 1 To access data element from a particular record we use base register to hold the beginning address of the array of records, index register to point a particular record in the array of records and displacement to point a particular element in the record. This is illustrated in Fig. 1.7.6. Fig. 1.7.6 6. String addressing mode : * This mode uses index registers. The string instructions automatically assume SI to point to the first byte or word of the source operand and DI to point to the first byte or word of the destination operand. ‘© The contents of SI and DI are automatically incremented (by clearing DF to 0 by CLD instruction) or decremented (by setting DF to 1 by STD instruction ) to point to the next byte or word. + The segment register for the source is DS. © The segment register for the destination must be ES. TECHNICAL PUBLICATIONS”. An up thnist for knowledge‘Microprocessors 1-94 8086 Processor Example : MOVS BYTE _; If [DF] = 0, [DS] = 3000H, [SI] = 0600H, [ES] =5000H, ; [DI] = 0400H, [30600H] = 38H, and [50400H] = 45H, then ; after execution of the MOVS BYTE, [50400H] = 38H, ; [SI] = 0601H, and [DI] = 0401. Addressing modes for accessing VO ports (VO modes) = Standard I/O devices uses part addressing modes. «= For memory-mapped I/O, memory addressing modes are used. = There are two types of port addressing modes : Direct and indirect. = In direct port mode, the port number is an 8-bit immediate operand. This allows fixed access to ports numbered 0 to 255. Example : QUT 05H, AL; Sends the contents of AL to &-bit port 05H. IN AX, 80H —_; Copies 16-bit contents of port 80H = In indirect port mode, the port number is taken from DX allowing 64 K &-bit ports or 32 K 16-bit ports. It is also known as variable port addressing mode. Example : IN AL, DX ; If [DX] = 7890H, then it copies 8-bit content of port 7890H ; into AL. IN AX, DX ; Copies the 8-bit contents of ports 7890H and 7891H into AL j and AH, respectively. (EBB The 8 bit and 16-bit 1/0 transfers must take place via AL and AX, respectively. Program Memory Addressing Modes © JMP (ump) and CALL instructions use program memory addressing modes. These instructions have three distinct forms : Direct, relative and indirect. Let us see these forms and corresponding addressing modes. Direct program memory addressing = In this addressing mode address where to transfer program control is specified within the instruction along with the opcode. The Fig. 1.7.7 shows the direct intersegment JMP instruction and the four bytes required to store the address 20000H. This JMP instruction loads CS with 2000H and IP with 0000H to jump to memory location 20000H for the next instruction. » An intersegment jump is a jump where destination location is from a different segment; it can be any memory location within the entire memory locations. ‘Therefore, intersection jump is also known as far jump. TECHNICAL PUBLICATIONS”. An up thrust far knowutecoe| Mlcroprocessore 1-35 8086 Procassor JMP 2000H Fig. 1.7.7 - Like JMP instruction, CALL instruction also uses direct program addressing with intersegment or far CALL instruction. Usually, in both instructions (IMP or CALL) the name of a memory address, called a label is specified in the instruction instead of address. Relative program memory addressing «In this addressing mode, the term relative is restricted to Instruction Pointer (IP). » For example, if a JMP instruction skips the next Sbytes of memory, the address in relation to the instruction pointer is a 5 that adds to the instruction pointer. This generates the address of the next program instruction, This is illustrated = oe: in Fig. 1.7.8, ano JMP {05} » It is important to note that in JMP ee os instruction, opcode takes one byte and 20003 H displacement may take one or two 20004 H byte. 20005 H 20006 H = When displacement is one byte (8-bit), it is called short jump. = When displacement is two byte Fig. 1.7.8 (ié-bit), it is called near jump. . In both (short and near) cases only contents of IP register are modified; contents of CS register are not modified. Such jumps. are called intrasegment jumps because jumps are within the current code segment. = The relative JMP and CALL instructions can have either an bit or a 16-bit signed displacement that allows a forward memory reference or a reverse memory reference. Indirect program memory addressing «The 8086 allows several forms of program indirect memory addressing for the JMP and CALL instructions, a In this addressing mode, it is possible to use any 16-bit register (AX, BX, CX, DX, SP, BP, DI or SI); any relative register ((BP], [BX], [D1], or (SI); and any relative register with displacement to specify the jump address. This is illustrated in Table 1.7.1. TECHNICAL PUBLICATIONS”. .An up thrust or knowiedge+e “Jaumpe t memory locatio location addressed the contents of the Sung we mer non mah nit of | Faced ush a « ((ex+1}, [Bx)) : dite High byte_Low byte. i location addressed cof the lolmeioial se oe I : the current code segment, z i TP & ((D1+3), [Di+ 2) bedeeteseieh High byte Low byte ae tore memory location addressed by the contents 2 Ne a eciends by ARRAY pls BX ] Gia te cast Gee pane IP © (ARRAY # BX + 1], [ARRAY + BXD, iu High byte Low bye Table 1.7.1 EEZEE Stack Memory Addressing Modes a In this addressing mode, 16-bit cantents are pushed on the stack or popped from the top of stack. For Example : PUSH AX POP BX Sena) Given that DS= Determine the physical address resulting from the following instructions. i) MOV, DL, [BP + SI] ii) MOV AX, [BX [DI - 04H] iti) MOV [BXI, CX io) MOV CL, [8734H} TECHNICAL PUBLICATIONS”. An up thruat for knowedgeMicroprocessors 1-97 8086 Processor Shifted contents of SS Contents of BP Content of SI Physical address on or Shifted contents of DS Contents of BP 1-06 Physical address 2 ee iii) MOV [BX], CX Shifted contents of DS Contents of BX Physical address iv) MOV CL, [8734H] Shifted contents of DS Offset Physical address REED is tring er fr the fing rat wh pi ‘eds generation i) MOV AX, IBX] [Sil #) MOV CX, IDH it) MOV DX, [1234] ie) MOV BX, [BP] [D1] [0045] Solution: i) | MOV AX, [BX] [SI]: Base plus index addressing. Physical address : DS x 10H + BX + ST i) MOV CX, [D] : Register indirect addressing Physical address : DSx 10H + DI ii), ~MOV DX, [1234] : Direct addressing Physical address : DS 10H + 1234 iv) MOV BX, [BP] [DI] [0045] : Base relative plus index addressing. Physical address : SSX 10H + BP + DI +45 TTEGHNIGAL PUBLICATIONS" An up thrust for knowledgeMicroprocessors 1-38 8086 Processor SE eee the following date in the registers : 2 AX = 1234H; BX = 5678H; Si= ABCDI Dis CDEFH CS = 3456H and IP = 789AH; DS = ES 167 a ee State the addressing modes used and work out the addresses of source and destination of remand di ata ey jailer ves a oo i i) MOV AX, BX ~ ne iti) MOV wor pr (BX DI + 56H, 9a ») LODSW f Solution : i) MOV AX, BX - agile sade This instruction will copy contents of BX register to AX register. AX will contain 5678H. ii) MOV [BX1, AX - Register indirect addressing mode This instruction will copy 16-bit contents from AX into a memory location offset by the value of EA specified in BX. Contents of AX - 1234H is copied to memory locations 4ACE8H and 4ACE9EH. Physical address iii) MOV word ptr [BX + DI + 3456H], 9ABCH - Relative based indexed addressing mode. This instruction will copy contents 9ABCH to the calculated physical address as, 16-bit displacement Effective address Note : As the offset address is continuously incremented, it goes from FFFE to 0000, which means that addresses wrap around from the end of a segment to the beginning of the same segment. Thus, when calculated effective address has a carry after 16-bit, ic., if it is greater than 16-bit the carry is ignored. The effective address will be the lower 16-bit of the addition. TECHNICAL PUBLICATIONS”. Arr up thrut for knowledgeEffective address: Physical address, iv) MOV AX, I9ABCH] - Direct addressing mode. This instruction will copy the contents of memory location, at a displacement of 9ABCH from data segment base into AX register. Effective address is 9ABCH, directly written in instruction. H pC H Displacement. H_— Physical address v) LODSW - String instruction This instruction copies a word from a string location pointed to by SI to AX SI will point to source string and copies word to AX. en ee a "made wrens for the fll inciructions ADD IDI, AL —_ti) SUB BLOCK, AX ii AND [8x 4 D CL. iv) ADDC {BP+100H), AX ‘Assume CS = 1000H, DS = 2000H, $8 = 4000H, BX = 3FFFH, DI = 5A00H, SP = 64A0H, IP = AQOOH, BP = 69B0H, BLOCK = 4000H. Solution : i) ADD [DI] , AL - Register indirect Real mode address = DI + DS = farke & o] H @oiy 0| H Effective address 0 H_ Physical address ii) SUB BLOCK, AX - Immediate addressing Substract contents of AX from BLOCK contents and store result in BLOCK. Real mode address=BLOCK+DS = [2/0[0/0[0] H Shifted contents of Ds + [alololo| H Offset 2,410, 0)0 H_ Physical address iii) AND (BX + DI], CL - Based indexed Real mode addtess = DS + BX + DI 2[0[a]o}@] # + 9|9 H Real mode address= [2/9|9/F F| H TECHNICAL PUBLICATIONS”. An up thrust fr knowledgeMicroprocessors 1-40 8066 Processor iv) ADDC [BP + 100H], AX - Register relative Real mode address = SS + BP + Displacement MRE Yo ano tt ‘SS = 0300H AX = DI = 0150H DE = 0 : psi brn i Shifted contents of DS Contents of BX. Displacement Physical address Lees H Shifted contents of SS H Contents of BP H Contents of SI 4 H Displacement Physical address iv) STOSW : This instruction copies a word from AX to a memory location in the extra segment pointed by DI. Since DF is 0, and it is a word string DI will automatically be incremented by 2 after the copy operation. TECHNICAL PUBLICATIONS”. An up Bust for RnowtedgeMicroprocessors 1-41 80896 Processor ‘Shifted contents of ES Contents DI Physical address ‘Therefore, the contents of AL are copied at 04150H memory location and the contents of AH are copied at 04151H memory location. After copy contents of DI will be 0152E. Flags are not affected by this instruction. ¥) PUSH BX : This instruction decrements the stack pointer by 2 and copies a word form BX register to the location in the stack segment where the stack pointer then points. SP< SP-2 = 0100H-2=00FEH 0] 3/0[0/@] H Shifted contents of ES * 0 O|F|E H Content SP [0/30] F[E H Physical address Therefour the contents of BL are copied at 030FEH memory location and the contents of BH are copied at 030FDH memory location. Flags are not affected by this instruction. CRED cin ta BX = 63A9H, 5I = ACSTH, DS = A500H, displacement = 2886H H — Shifted contents of ES H Content BX H_ Physical address if) Register relative using BX Effective address = BX + Displacement 6/3f/Alo|H Bx Displacement Effective address: Shifted contents of DS Effective address Physical address TECHNICAL PUBLICATIONS”. An up thrust fr knwoMicroprocesscis 1-42 8088 Processor iii) Based indexed Effective address = BX + SI ra 5 [4[S|o[ 0 [f@] H — Shined contents of Ds + A,B] 6/6) H Effective address: 4([F/8|8|6| H Physical address MOV, DL, [BP + Sil ii) MOV AX, [BX] [DI O4E{] i) MOV [BX1, CX io) MOV CL, [5734] nig Solution : i) MOV, DL, [BP + SI] ‘Shifted contents of SS Contents of BP 0 * [olalal2 Content of St 2/4/31 8|2 Physical addross i290 TECHNICAL PUBLICATIONS”. An up thrust fr knowledge‘Microprocessors 1-43 8086 Processor ii) MOV AX, [BX] [DI - 0451] Shifted contents of DS Contents of BP Dios Physical address exer ili) MOV [BX], CX 70 H_ — Shifted contents of DS 4 + 0/3{F[0/0| H Gontents of BX Dla |6 [0/0] H Physical address iv) MOV CL, [8734H] H_— Shifted contents of DS H Offset H Physical address [pic] (GENEEREDD iy te arog moe fe instrction gen bw and jaiiy te Pera ie aaa 1) MOV WORD PIR [Si], 5 fi) MOV DS : [1000H], 10H ii) MOV AX, Num (BX + DU Solution: i) MOV WORD PTR [SI], 50 : This instruction uses register indirect addressing mode to specify destination location. Because the contents of SI register are used to generate effective address. ii) MOV DS : [10008], 10H : This instruction uses direct addressing mode. Because the effective address is specified in the instruction. iii) MOV AX, Num [BX + DI] : This instruction uses base relative plus index addressing mode, Because base is provided by array name Num, BX register provides first index to array and the contents of DI acts as an offset. (ERTIEERIEDD ldentify the addressing mates ofthe following instructions. TA MOV CL STS + 2110 USHA ee eine: Solution : i) MOV CL, LIST [SI + 2] : Register relative addressing mode ii) PUSH AX : Stack memory addressing mode iii) MOV Dx, [DI] : Register indirect addressing mode iv) JMP BX : Indirect program memory addressing mode. TECHNICAL PUBLICATIONS" An up thrvat for knowledgeMicroprocessors 1-44 8086 Processor (GRTIEERERD Bring out the difference between MOV AX, BX and MOV AX, [BX] (EE 2 cn oe i rn i ‘NEG BL i ADD AL, BL ‘ CMC. Solution : SUB AL, BL (CUSED 1 Ds = Apsoti, cs = o96011, 85 = sbooe, BP = 7E7ah, SP = 01351, SI = 1245H, DI = 4356H, then determine physical address of the following instructions = i) MOV [BP + DI +6], AH — ii) ADD AL, [5036H] Solution : i) MOV [BP + DI + 6], AX: i [slalolo| ss. 7 E BP [ats ot oo 6 falz[a] Physical address (ECEEIEEAD) Determine the physical address resulting from the following instructions: i) MOV DL. IBP 4 St} i) MOV Dl, {BX + 10GH] i) SUB BOX, AX ia) MOV [BP + DI +5], AH 0) MOV AL, [50367] BP = 7000H, SI = 0350H, $$= 8000H, BOX = 4000H, BX = 4FFFH, DS = 2000H, DI = 6A00H ; : ! Solution : i) MOV DL, [BP + SI] f H. Shifted contents of SS | H Gontents of BP H Contents of SI H Physical address TECHNICAL PUBLICATIONS” An up thes! fo knowhedgeMicroprocessors 1-45 8086 Processor ii) MOV DI, [BX + 100H] 2 H_ Shifted contents of DS H_ Contents of BX H H Physical address. iii) SUB BOX, AX Shifted contents of DS Offset Physical address: 2] H_ Shifted contents of SS ©) H Contents of BP H_ Contents of DI 0/0/5)| H Displacement [D/A] 0] 5) H Physical address Explain with examples, different addressing modes of the 8086 processor. [ Feb-05. 08. Marks 10] 2. Describe the program memory and stack memory addressing modes of 8086. 3. Explain with example following addressing modes in 8086, i) Register addressing {i) Base plus index addressing iti) Relative program memory addressing ix) Stack memory addressing, 4. Explain the following addressing modes with example. ®) Direct addressing ii) Register relative addressing iii) Port addressing fv) Relative program memory addressing. 5. Explain with example following addressing modes in 8086 : i) Register addressing ii) Based indexed addressed iti) Variable port addressing to) Stack memory addressing Leo & Describe the 7 data related addressing modes and program memory addressing moles of 9086 with an example each 7. Explain the based, indexed, base indexed and relative addressing modes of 8086 with switable iagrams end example. TECHNICAL PUBLICATIONS”. An up thst fr knowing