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20 views7 pagesARM Part 1
Arm tanıtım
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0% found this document useful (0 votes)
20 views7 pagesARM Part 1
Arm tanıtım
Uploaded by
lessons.for.self.improvementCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
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a oe
. venainianimiatin
i] Battery power Devices exs health moni fi
Fitness Tracking. »
2] Automative Apps.
ToT Apps.
1 AMobile& Home Apps.
5) home & Building Automation.
4] Tos KGrnsumer product.
fe Kmobile Accessories:
Test measurement Devices,
‘eimnst of the Pomous MCU manufacts
prduclng Mts based on ARM*
el BULey (o
UTI + Texax instruments
“Lou, Baters Based Apps.”
fewer
AsTsu ight medium +Low Performance
Meu
Feshiba> measuring Equipmedts Rmeters.
A NXP
FMicrochip
D Boarel Cmmunication»-niteless Connecti
Dits minimal Cost.
ZA minimal Power
FJ minimal Silicon:
A3I2LIt processor will lost
Gmputational Performance. with
the Same PYice of 8 Ki bit Processors
DUltra Low power to High performance.
based fas anf
Di process is Customizable include.
FRU, DSP, MPU, ete.
very Posertel & Cosy to use nterruph
cuteller wlach Rigjer Suppor” FASS
Cee a rp oegtion
ae rte mera Ht provides
Syckem Lnception 5, Pocessol”
od Modes» Access level
Configuradion, Stak Medel helps
ckvelap secured RTOS \elatal Affs.
Bthes Induction set ig Rich &
CNPiciedt, it uses Thumb
inchnation Set (AG BIE), ARM iashuct:
Set (32bit).
Now we Use Thumb 2 Instractionget
Llé bit &32- bit] .
* most Uses”
ARM CorfekM Cannel Excute ARM
ingtudtion Set, it uses Thumb2. insta.
which gwe the Sane Cf ficiency
Powel” of The 32.ARM Set but
in [bbit Arma.
BaARM provides alato? documertitin
TD & Refere
nce. Manuals user Guide.
Scanned with CamScanner There are 2 Architectures =
WVon neuman & [21 Harvard
TI simple in SW
4 Hw
TD Complexity ia Swi & HW
QExtra pipline Shge Fe
B Miclocorttroller Architectures: + Tn AVR Alclitizcture:
For fx: Porth X20 (ora
* Cmpbxity k Extra Hey
Voy 6 Harvard Aids 3/Ls 38 ak jae
Byag AMRIT Ty 6 Pipliniag tl B90 Get
“sat 2 GALsit 9g Had OF
Al log 6 te ese) ce :
mera sad gALAcals © os 9
arity
last tev Sey Set ss RS
0 rt
feared leg) lel SS ul
sADL9g Ale eae ne be
Do Jags Oi olils Assen
* PevigheFal
x data Bus in AVR “to Flach is WEA
*n ou wu te RAM 1S 8 bit
#I0 ARM ARdhitecture:
aiictualy one Bus
suriting C, you Can access any
memory.
2 USing pipline of Harvard .
DB
Scanned with CamScanner xlecd > memory map
Explanation of mopping of difPerentt
Pleriphetal Registers & memories In
the piocessor addressable Fegion odepend
on Size of address bus, This (Scaled
memshy imp.
(system Rus) 32-bit
This adress bus is 32 bits, se it Gon
Access Uts 4G Locations Skyting
fiom o > oX FEFF FFF
memory Map;
+This Regions are Cited,
by “Tre procegsot-
designer, Can't be
Changed.
| # prospem (ode Could
| be Doel Fram SRA
| Region.
Code Region :
coe > oroxdilt FFE
Code memory iS Connedted here 512MB is
Very Big Por most Vendas Connect as MaX1ms
eusually for bigger Cade memary than MCU
internal Flash y we go far External Flash.
| © Processor by default fetches instructions
vector Table information from This Region.
ediedly after Rest , You Can change.
| this by the best Pins of the Me.
GISRAM Region : on
— Next 5I2MB 5 oX2or0 oo —»oX3SHi FPP
— mainly for Connection of internal SRAM
— 15 49g of the SRAM Region is bit
bandit Region “bitaddtessable Region”.
x(Us ¥) (love) \-t<«o 5 ‘oXtoeo
Read y modify write [2
oy PL ES
tek 1c 10K Feat
ABeleck Cycle to ovitel
#(U8#) (20) =4 5
\, L clock cycle.
~ bit banding Cin be. used for bit banging
* Stream of bits”
Bl Peripheral Region :
~ NeXt SIZMB-p of 4ocncace > XS FEF EEE
-used mostly for on-chip peripherals
—Like SRAM, 15f 1M of This Region
is bit"bandigy” acldiessable Region.
xn iP the bit band Pechure inchided x
Processor peripherals arent here (wic-]
This is an Excute Wever Region. xe
— Tying to Excute Ge from this region
Wil] Tyg ering Fault Exception.
— Basically this is to Prevent Gde
injection alfacks, Like S8 Can
ttansmitte Code threugh the peripheral
& make processor Excute the Code .
Tet
Scanned with CamScanner #Suppase You Need more RAM for yout”
Prijedt, i.e Some Graphics Yelated Projet!
Se youCan Connect Extemal RAM
to this Region. #Cin Excite. de. -
& Extemal Device Region:
*igGs.
— ited Intended for Oxternal Devices
and ot Shaved memory «
# Exaile Never Region #
= This Region includ [NVic,SysTicly ScB, J
— Excite never region. Gn)
AL Extemal RAM: [> Aue QAPB: Bus Protecel ‘
4A-ANB Lite is mainly Used for jhe mair
Bus interfaces
2-APB is used far PPB Access & Gore
on-chip Peripherals yusing an AUB —
-APB Bridge
3- ANB Lite. bus majorly used For High
Speed Communication with peripherals
that need high operation speed
4-APB iS Used for Low Speed Gmm.
Compared +a ANB, most peripherals
that dt rue Hi pr. ae
Connected to APR.
| mProcessar qves oat 4 bus inferfaces: ©
ARM Provides LAMBA] :advanced Mc Bus
Architecture, standard for on-chip Comm.
+AMBA Suppor Several bus protals:
1-AUB Lite [LAMBA High Performance Bus].
2-APB LAMBA Peripheral Bus],
4 OW Chip Communication Means Communic
between Processot & memary peripherals.
[Zener speci.
|
#ZBAHB buses KLAPB .
H 2buses jierfaces for the Cade Feyion!
" T) T-Bus + used for instruction feteh
k Vector table Read
T] D-Bus: Used forrdlate Access ia
The Cade Region Lhike Const]
2S fetching oatah Instruction Gan be
Ohne at The Same Teme #
S-BUS Vari. bus on Chip peripherals
memories.
oe for Core fori heral
Scanned with CamScanner WPRCesser vs Processal” Gre
wIneide the Core:
4-ALU Ea
2- Deade & Excute Circuit CU]
3 — Register File
4- Piplire Engine
M3& M4 only have One Gre.
\— Operational Medes
2-Different Access Level
3~ Register Set oP the Processet
Lore RejisterT.
A banked Stuck Design Tstack
Mematy handling 7
5_Exceptionsk Exceptions
Harling.
6. Tikerrupt handling
F Rus Tnterfoces & Bus Matrix
8- Mematy Architecture [sit Banting
Amernaly MOP z1+ + ~ |]
3-Endfanness
lo- Aligned & un Align ect bata
transfer,
i-Boot Loader he TAP Pregtammiag
(Operational Mode ef the Processat
[Mos Ma, Mal .
TH Thread Made TAKA user Medel.
Bl Handler Mode.
UT All your Code. tefll Fun [excite] under
Thread Mode of the Processor’
BIAll the Exception hentlers ESR]
WillTun under “handler Mode", e ther
ea
3) Processor always Starts ovtth
Wread Mode.
Whenever Is® Sprts, Core. Cheng:
Ths mee t handler ode.
TAI handler made. you have Fat
Contra over all the processot”
2 stem Level g Register, Trferruph
Config.» Carttol Registers.
In “Wittod node, You may have.
Cortral oF You may nar Ihave Gortral
depending on access Level:
tl
Mls
Scanned with CamScanner TD) Precegsar offel 2 access levels PS 9° PAL
1B Privilaged “fevel (PAL)
WH non privilaged access Level
Leal]
Aly your Gade is Tanning with PAL
then your Cade have Full access to all
the Processor resources restricted
registers, system Level Fegisters
Unich are pretacked by the Processol”
It sel By
Bi iF your Gde is Panning with WPALS
D when a user Pragtam goes wrong ,
then gar Gse May ae access itu vot be alle & Crrpt Catt
tf ee ed registers Resher'ss mest Common. USE in
: i RTOS [Kernel & Tasks]
By default, youl Code. usill Pun in AAL A oe
EIMPU Gan block Some regions
Prom Pragtam USer-
luhen Processor in thread mode
| it’s possible. to move placessor fo NPAL!
| then if not possiblete get Ht back
bt PAL, unless Plocessot Changes
to handler Mode.
B Handler mode de. €xXeution is
always with PAL.
Fuse the CONTROL register of
the Processor iF you wart tosuiteh
between Ahe access levels.
El Tn Handler Mode You Con Qnlig
| Whether it will retum on PAL
oY NPAL.
Re
Scanned with CamScanner Ro —sRi2 (GPRs)
| TA aly Cove. Registers are S2bits Sig
Re is Glled Sh (stock printer),
use te track Stack memory;
PSP Process /Prgtam Stuck pointer
xMSPS Main Stack pointer.
#BanKed Vergfions of SP.
Ria iS Called LR (Linked Register”),
Used to Seve the Teturn info Fran
TSR ,Subpitine, function Call.
By Program Qouttier-(Pe) ,Goatelins
Curent progiam acklress, BAT O]
of this Hegister Ts Loaded frrbo
EbitA must be 1. ,
TE Ro
a
General
Purpose
Registers
sees) [PSR ][MSP]
Linked Rejister
PORE) [Prerem Resster
‘Sfecid
, Exception
mask
reisters
bL: Winch with Link
update ec & LR
| ta spectal Registers :
5 Reyisters [lps »PRIMAsk
BasRIGA
BASEPRE, Cour]
FD PSR: Program status Register, hold statis
of Curent Excatton of the prsyram
this Reyister is Collectfon,
of Bdttferent beyisvers -
TARSR: 7 Stus Register
PASRe Lert pig. Stehas
Registets Grikai ne.
TSR number.
TERS 2 execch ioe postom stati