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Z- tro — Te psolt is rer0 5 -prequecat £ AD indice equality - # rered B31 Of the zesut ig g Besta 90n + ‘Page No. OB... ‘ : ‘ij 7 oufference _bbe“tuecen ty Micra conttolles ancl Mic6o processor | iy RISC Aud CISC r aud Micro conto Ne 3 = Clecttonic comporent “hat _ py wien processor an pomputet 4p AO its work: Ft is OCEALIN: voit Ce mg [iateg cigeult chip _Cpataining _mi Winns of | mall _evmponents intlveting- -teansistors , wesis toss | | vesy SOAS Aner: and diodBs -that _wowk A micgocontgoties 7 com pac Integpecied civouit = iqned 10 aaa cific operection in et pal embedded tems | A typical enicsocontvolley _inclucles _c PeOCeMOe memouy tipheval_on _& single Chip: and input foutput (Tlojae rae M1 trope Mictocontso! ler NilctoPto cessor pincer’ newal obo, ct inter ted fee PeP0e bios, ae ei jocludes a PY, “unit theck oniy COO ang memor (Rara/Rom) cond tthe CPU and Pequitey | pesiphezals on & single Chip — extegnal Memory. end} pesipnersis: | | pu, RAM ,ROM, Tio Posts and pezifpners!s on 4 single Chip: | Only Ihe CPU ic Prenat. | memory (RAM/ROM) and | | peripherals A¥e Bete. | ou | i Higher , veqeiira Move | seniged 7 bectoler{ : opr gee Power Ave ty Oxterns) System and bv treng rye Compones | powered cepplics hang 2 ae ed Hguer Procesting power, | Dewgqned for Specific” ‘ COutsol tasks 5 capable of wnning compicx limited processing Povete “OS I'Ke Windows oF Linux: a eX gn Wes inpuit Pash] wii team and EEPROM and RAM fov — Stosages proge.m and dale Cpst Gye ness!" Chres per = all components ase on Single chip: Sms and Compre:At9e And Complex 4g aL cally nigly Ophegect xt | 4 touctiong ie matte chon : simple ineloding wor Poses erecuion duet Siowes execution Os inteuch yele Westvvetions CAN Fake mo lpi copes ao ae | e9 Vagiabe - eNGth tanh ‘adstouctiong mote initio chm, ewes ONOVG UIT indteuCBiong | eduGng Hernovy uAAHEs g wires ferser Eefistees , BELA MOK On MENU CY 08 Opess‘hous Oifficor to impiement pipetiaing due 3 TE wit¥uction execeien tne comp ex quehi tectune tants , Ino consump? :“6 {B.. Explain the Grenitecture of an arm embedgs ’ F device with a next Sh agra: ARM Procescd r Memote Controller | ARM. procesor bared embedded System hardware can be Seperated ‘ato the. Jollowing four Main hardware. component: >The ARM protewso7 + The ARM Processor contsoig the embedded device . Different yerstons of the ARM proessor aw cyatlabie to suit the Oesitted Opeeacting Characteristics « iy f I> Contaollers + aewoleirgy tontroliers the system» Too Controllers cre foley «Page No. ..OF...... eA bus 19 wed to communicate between, pasts Of “Ihe devites mm Bud Technolog S Embedtded devices _wre_qn_on- Chi bus that's | Seteenal_t0__‘the chip and that allows different peviphera! Gevices 10 be interconnected with an AR coee prea Bus P otoco |= She Pavaned Mictocontoolier Bus Michitectuse (AMBA) | hoa been widely adopted ab the On- Chip bus _cBchiteciy usd for ARM procenors BA busch Iuttoolured useve the B) and ARM Peripherc! 88 (APR). D have Some fown of memary ¢ ry cache is loerted St, Secondary d my cove, the Smelly| * Peripherals - 3 ‘a tems thet tatetact with “He outa; —s Pmbelded sys RB gail, clei Si] Neect some form of pes'p Spemory Conirier Memory Conor onHl city, | typ of memory +to the processor buy + | ‘ | = Do-eaiept tons piled Ne interrept ConMOMES biovide | a pragemmabie governing policy that aliows } spore tu ceteaming which pesipreest OF Aevice | a vaverruph the procedor At oy SPER wh, | > How ae moaitos and control interval operation; pevforaect in ARM cove 2? Explaio in baief + he ARM Core urex the CPSR +40 monitos and eontiot iatetnal Operation + CPSR is cutteat PTR” Status Register which | te a cledtiated 22-bit wep stew which Tearides inPage No. 09, 0. a Ga’ eenarled OLeMOTS*, which execites tC, ngtauctots * gibt ane censor Mode determines which vegistess are __| ous te yeast eignifiernt 5 bits de-esmines the | a al cewos Mode ts ether Awileged oy 0n- Each pe0 ces in {04 ne _ co - A 1 poacesor moods tw -fatsl~ _Sin_privilegect (Abort, | yisod System 4 intetept intettupt 14+ ancl vale fined Gndl OMe - Non-privileged! Mode (Lacz). =onal Tastyucton Sets ‘+ The ctete Of the as egmings wich imstyucton is being eXeeirted | are 3% lnsise ction set ARM, THOM, Taree. tevenoms ts only wali foetive when econo, M Sterte. + Simiiarly Thumb bngtroctio9 se+ is ony 0 Kinds of atolwewe. Her Iapre + @)and Post Intersupt Request(r 19) | (DPG is disabled Ault causes 4 giqned Overton, an ungigned carey ese : frequently uxeol to F causes an ouerfio, encted |Page No. ..! neat _ otic gam explain embeetoled gue Aeviter, cltivets citcults Talento PE [eontaot tes 0 EI = Toerrvchon : | = Meximom bits of |4 Source — Tntesnal Power supply is must ive pen powcr Up % po wen Fon conBavougt ‘ons System consumes 045) ar hence ef fieten¢ geal Hime programming by i 3 ‘walt’ and © sip’ Becton of ne unit whith ase not in WH, Cay sly! pout consum phon mes, axed CPU machine Cycle clock | execotiag 2p iitivctons. na) ot extextal. Jf hold be | | ting various Salts jr | algo uses! fo¥ olaivingoP ene ond 48 evi a ig gly WC* pam cows have 2 cli pectcleA_system often we multiple memory 7 peccensauy “to have Q method fo help caganize, me ceuiees and protet ‘them fre System from applics tions} we to make _indbb76! oT gemeiued with the helb Of memdiy mancqnedt ment in FIRM cove - Comba, iy —coupleal memory { (coe Extension of | AR] jate ACO tp hatdweses iont types Of memory mancaceredt f ; eee é pagawate — 20 extension [pidviclna no protection) TS q memoty paoteot jon uni (MPU)[Paovi =a ste DA Memety Marege at Unrt (MIM) (Péovietng lemoty is fixed) and provides ver Uoritect Pzotectivn) Lott Peoreehon). U is O08Mally wsecl fos __SMs!! at strat _Fequise O0_peokection sthat Ureh © limied Tee veaions ave _combolk wegistey_, and _eact CC€ _pesmission: d for sus-ems ©. complen_ memory |ge in) MM Ug I { aie “the § most COMP¥hensive — Mecigy; Management hasdwase available on the feo MMU tues a get of translation tables 40 broyici., tine ~grined contyo) Ove7 Memory + Cache and Tiqutty-Coupled Memoty - Cache ig wlock of fas memory placed betuccen main memory and comes tUriIh & cache “the poo cexsoy Bore eenton for moatority of the time without hay, to wait for date. from Slow external memowy « ‘t ARM hes 4w0 form of cache » The first is found ecHached +0 the Von Neumann style coves « Ftombines both data and inghre ctHlon into. a Single bnified each e-cavne _ppdoviles AN overali ineresse in bevfoumsnre — xt exbente of fy Aictable execution « Ba Hime Systems i+ Is paramount ~thet code ereeastion epminstic = the time 4aken 1_loeding ang lastevctions ox data mus! be nt eclickabie- OOM Of memory 63 Ned ¢'¢ \ + Exp tain meoheniém applied by ARM core to handig\ exception , intesvepts using- Ufyperent vector Keble. D> When anexception of intersept OCCVIS , ~the Procestyy | stts the po toa spelific memory adaters The Colel, is within a She cia! ange eslled “the vector tebIe, | "When an exception ov inestopt ICCUS , the brocex op, Sugpencs norma! execution ‘anol otarts picting fastovet, from the @xcepstion vector -leble- | Each vector tebie. entey Containt a form of branch jastavetion pointing to the Siavt of specific Yoetine ; % Reet Vector ig the location of the fitst Instevchon | Gecvtecl by the frocesov when power is applies Thic instruction teyenifies to -the IniHaligation code « 1) wodefined tnctzucton Mecho? is wed when the péocesor Cannot dleeode An instruction. > Scfuoaw. intereapt ect is ealled when you eveeute «| Stor instavertion - Re suoT _lnstreetion ured as the mechanism to Tovoke an 8s preg ueen: Obevating System woot:Date...... Page No. .. =... } y inersupt the nosmal exeayton tow ofthe byocexor. : Tao only be Baise it TRAs ate not masked in 7 ne. cesR + I S a Reset RESET DxOCLOL000 OXF EE EODOO undefined tastrvction UNDEF © x00000004 Oxf 4740004 | TT] eoproase Dntertept Sor 9x00000003 Oxfyt 0008 | Prema aT eae cre pats fibowt BART Ox00000010 Oxf FFF-0010 Resesved —_ Ox00000014 + — OXFFFF OD14 [| Betertupt Request PRG OROWOE Oxo Past Tntereept Request FIG. Oxo00000!c Ox FFFFooie & | Explain the ARM olesign pwilospphy — I These ave _a number Bf physics! features that have asiven the ARN pgotexer clesiqn: a | > Postapie embecldled syctenn’ equines ome fore of be: . ifs | Tete powers The ARM jwocexoe has been Beato L| destined -to be gmall to weduce powes comomphon and extend beHey. ton — exential Nescbions - p28 extend barter “Obevadhen—ekential for applies ties | H> High code density is _a mejor wequivernert ince embectdec a have Umit memory dee 40 OF physica! She westeictions Hign code density tg _wsefol fov . &bplications “thar have UmMe on-Gased memory ,SSS Perle eS Tid Eanbesteted ARM hat Tncosporeted Heelwete oleh procemor go thet 80f-boave technology within lhe t ongineeas cqa Wiew whect ig parser: saat the procedsy, i 7 i effecton -the +, 1 oti des This adios cline sn tid ee pecuees overall clevelopment costs « m sup Th ARM , for a Single chip solution ,the Smatiey the aves veect bs embeceled processor , the more available spste for apecintiget peripheral: This. in turn fewer ctiscrete chips ove vequited fos IPC enol bFoduct. 2 Deseribe the RISC design philosophy with design woke. => The ARM cove wes qa RISC architecture « Rise $$ @ detign philosophy aimed at deliverin simple but powesful instructions that exe cite Shin a single cycle ata high clock speeds 1“ j 5 “The Risc_ philosophy. ts implemented with fout major desig nro les $= " Tastreccon: RISC Protekers have a aedutel number Of insttuchon claser- “there clases provide sieple La “oi aa oh exeeete in a Single oyeles ThE compiler OF forogmmmer gy nthesizes compliested Opesstony by compinins erin Yeruction: yeaiuees the cost of the olew'go and manufactvting eioee |iaes— The pzocessing 6 down into pasatiel by insttvetions ts token mnatier vnits that can be execotd in : ibelines TMnsteoctions can_be decoded in one pipetine_Stage« pegiste¥, RISC machines have a_larger genera) mnpose waists Seb « fhy wesisiey esq contain either data oY AN addres - al Registers act ag the fast locs! memory stove fp Fall date processing Opetatons + ta me Arohitecte - Bea: pn data held in seqishers « ancl stove _instouctions transfer cota istex bank and _extesns!_ memory» pi cosh! 0 a ahi menor g d protein. psovides cin. d wean use dota items held banks withowt nrecting