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CompArch Midsem

computer architecture paper

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57 views2 pages

CompArch Midsem

computer architecture paper

Uploaded by

priyansh.contact
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1 Computer Architecture (CS F342) Semester-I, 2023-24 Midsem Examination Department of Computer Science and Information Systems (CSIS) BITS-Pilani, K K Birla Goa Campus, Goa, India. f 11 Duration: 1:30 1 ‘otal Marks: 50 Instructions: Every question is compulsory. For the questions, no marks would be awarded if no reasoning is found in the Answer script. You must write all answers fo a question contiguously [not here and there within the answer script, (@) In the 32-bit single-cyele MIPS processor, can we set the “rt” field as the destination instead of the “r vice-versa for R-type instruction? Justify your answer considering other instructions (b) How do we generate states in the hardwired-based and microprogram-based control unit? (©) Do we need the opcode in the special-purpose processor? Justify your answer. (@) The 32-bits 5-stages pipelined MIPS processor runs the program described in Fig-1. Which registers are being ‘written, and which registers are being read on the 5th clock cycle? (©) When silicon chips are fabricated, defects in materials (silicon) and manufacturing errors can result in defective cireuits. A very common defect is for one signal wire to get “broken” and always register a logical 0. This is often called the “stuck-at-0” fault. Which instructions fail to operate correctly if the “MemtoReg” wire is stuck-at-0 for the 32-bit single-cycle MIPS processor? (f) Can we take the forwarded data for resolving the data hazard (R-type followed by R-type) before the stage registers, in the 32-bit 5-stages pipeline MIPS processor? a” field and (Marks: 14241424141] . (a) A 32-bit MIPS single-cycle processor fetches the instruction word: 0x0800248C, What are the values of the ALU Control units inputs & outputs, each mux’s (Mi) inputs and outputs, input values of ALU, and two add units (Ai)? (b) The logical blocks to implement a single-cycle MIPS processor's datapath have the latencies in Table-1. What's the latency of an Retype, LW, SW, and BEQ instructions? What’s the minimum clock period for the processor? “Reg. setup” is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both PC and RF. AL. [Marks: (1+5+2+2)+1(4+1)] (a) Consider the 32-bit single-cycle MIPS processor and modify the datapath for “sra $rd, $rt, shamt” instruction without affecting the other instructions. Write down the modified datapath and Verilog code for the modified units’ part only. The instruction performs shift right arithmetic operation on the value stored in the register named as Srt and stores such value in the register named as Srd. (b) Find the CPI of the code snipped presented in the Fig.-2 when running on a single-cycle and a multi-eycle 32-bit ‘MIPS processors. (Marks: (2+4)+(2+3)] 4, Design a system for the incoming bits (0/1) from a testbench. The system will provide output “I” ifit processes an even. ‘number of 1s. Otherwise, the system will produce output 0. It will produce output “I” at the start of the system. Write down the behavioral Verilog HDL for the testbench and system. [Marks: 8] (The MIPS register file should be expanded to 128 registers, and the instruction set should be expanded four times. ‘What would be the effects of this on the size of bit fields in instructions of type I and type R? (b) The designer wants fo add “Iwplus $rt,imm(Srs)" instruction inthe MIPS multi-

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