Unit -2
Semiconductor Memay Tntou7acigt
Semiconducte mem aies ace
DRAM (Randsm Accey Hermou)
ROM (Read only Hemoy)
stati RAM Tntentacing
he omiconductoy RAMA aHe
ypes - statie RAM and deanmi Ram
RAm and Rom wth 8o&68o&&.
Fo example 4kx8 oy 4k bute memOUy
(ontain 4096 locationbheegch loatíon
Contauns 8-bit cata selesLone
4016 lDCations Can
Can be
and mly omeethe memin
e the
be selected att a time
Drce Olocatin is &elccted au the bit nit
acesiblc uing
Called dota bus'.
a gtoub o cndutos
Obvjpusly fos addeonng 4x byti o memay,
tselue addsieno lnes ad Hegued
In qencal, to oddues a
memey aation ut
n bits of egLixe atheast
oddos, -e, n adaOs (ines Lehee
nLog,N.
Thus , the mNo paoCead y has m ddeess ines,
then n able toadders at the mot N
locaiom memory, ohee 2=N.
lo Catios only
DA TE ...........
IAGE
location ae to be interfoued, hen theha
tnes out of
east siqnificantp adduen die
available mines can be duutly ty conneced
om th micopocsoy to the meny
chib tohil the omaiming (np) addn
Bdee addues tines mayb e d o
decoding (as înpeta -to the chi gleltion Loy')
he nmou aaldes depengs upm he
haydoae biuit ed yon deioding he
chip select (a).Th ottthe thecSdeloding
pin o
pin ok
cHuitis onneed eoith
the memey chi
mamamy
+ The genenal pHocedus o statii descuisbda
Intexliing with go86ú baielly
zollouss.
tuange the avai lable memay chips sa auto
obtoin l6-bit data buus
bank i caed otd adldseA memgy bnk
and the loue 8- bit bank is caud een
addes memoLey bank?
Connet auailable memoy addes lines e
chips
memgy chips sth thoe o the micxapci
ond a Connect the memos RD and lwR
in puts to the coenponding ron
Csnbuol sfqrals Connect the )6- bit ala bus
co the méme-y bank torth ht o the
milMopoclsO o86.
he Aemainig addess lines tie mispas
BH and A e ued the
NLguMd chip select siqnals tos the add
bahks, the Cs
memneodiy
the
Let
puoblem
cincuitl
mos Cm siden a eo examphe
'ODblem tw0
Jntehae too YKXR EPROMs ndsuitetto
4KX8 RAM chips cith g0R6, Selet
maps
Sol- we knos that ate eset the Pand
CS ae nítalised to dum eldexs
F£fCoH. Hence,thís dden must le m
he ePRom. The addees RAM may be
Selected any whee 'n the mB ddde
space L RR6, but e wil select the RAM
Laddes such that the addues map o the
fPeffH. 1
foFfeH| o
RAM 8KX
DATE . . . . . .
FAGE
ODD
Rom Ap Rom
A,-A2
A
3:8
RAr Ao RAM
Ao
A A
Pp---Ais D,-Do
Dg-Ds
Total 8k bytes
A-An (ihd e g3oerROm
k).
med 13 oddsans ines
Addos lines
de Coding to geneseate the chipA4
sclect -he BHE BíqnalOaoes loo ohen a
is at bdd addtes or híqheo byte ol data tooner
is to be accesed et sne tht the athod
addeoss. BME and demuliplex ed data ines Aue
MAdily availake jo iy fige ihoy
he inte7ocing diagrom o
he memgy ysBem In thia erample Cantain
in total on KX memoy Chi ps
Che too 4KX& chips e RAM ondl Romave
aYHanged. în paxalel toobtain |6-bit data bus
usidth I A A O, ie. the adoleex is eien and
is n RAM then the <ousey RAM chip fs elected
indicating g-bit buanahe at aneh alales
Ao i64 ie the addes is odd nd is in
RAm the Bné
BHE goea loo, the upbey RAM chih
ia alected unthe indicating Aht the -sit
ranste is at an odd addues s the eleced
addslenes_ae in Ron, heespectie RM chies
ane selecded, d at a time
aue o, both the RAM o Rom chips
ie the data anseu ih o 16 bit,. he selecion
chips hene ta kes pla ce as shoun in Table
LATE
PAGE
Table
Memos Chip Selectfon for problem
Dcoden IÊ Selection
BHE Caroment
Ap
Esen ano odol adaew
Only een aeldrsy
yte tang
Only odd addes
inRAM
Euen od odd
adoloes in RDM
6n DDs
Byte Zransie Ony ee adduen
nly odo odde
DATE..........
PAGE
katic Randor Acccs Memary (sRAn)
A stati RAM is a uolatilo nemGuy deuice
ohich means Ahat te Content, o e
DwYay wil be lost i pous
Dní& a dynamic mnou ornoed.
is dormowd
deuicc, he stati
does mat guiu a peviodical sues
Cucle &hd uns mch tester han
dnamiu emodsice
HLad) sito memgy s selai vely Srau, today
a Small memey byta
The main dibbnce betwean Roh ond RAm
is that RAm is csitten undo Mumal
Bbeatonm, wheeeas Rom is pogommed oituil
the campub and neually nly ad.
Dyramíe Kandom -Acc lemoy (DRfm) ’
’ Ailableuto 26 MX& 2G bib)
DRAM is eisetially the same s SRAM, ecept
that it utains dhta ko Snly
an integatud Caactn
A{ter H4 ms, the conterts the DRAm
must be Completey Aluoetten (sufeeshad )
ecause the tapao, ohich stae a loget
DRAM is e highest deaity, louiest cat
memoay CUently unlable . Fos these Hiasns
ti uiuessaly
based ystem mat
ed in lny mlsageCea
mAe than a
DATE .................
PAGE
a m o t tb m Volatile wsitable Stota
ma
pey ccl ldain acta as capacito)
>he tanstoy
Veoey g mall chavges Tnvolued cletet
otec
pechaged tD
bitines mut
bit aues ines is Small:song e
n bit leaels
Vottage soing to
ampAQgied destuutse; pRAm
eas ad tsto Os vas
ete data back on
c e e t can ip
data ill be lost
millidecsnds a andsize, DRAM
ckage cost
oeedue pin c n t by:
duices mimimize
nd coemis
sing
mutplng the
acldcesses
betuseen 808%CPUL
on inteface
stauting addxes
the
32kX& RAm. Select KAm aoss mest
ERom suitably The
t a t O000OH.
o
SoThe last adduen in -the he map
pocDceSoY Atants
adasces muot lie
Hence
1om
Ín the
F addres Mange q
DATE.. J..........
PAGE
-)6 KX8
Cuo Rom chips 32K
6kx8
luoo RAMs 32 kX8
32kX8
memguy loatioy
ines
fmIS’ adde0m Lines
chipseleat Pis-Pyg
64 kB
fAy-Ay4) ey chip slect
Addeexs Map
)
32KB EPROm
DECfHo
His bettey mot to e a decodex to imbleat
the cboe mab becaLe it , not csntino,
"l. the is Sme unsed adalcess pae tueen
the last RAm cdecess [o ffffH) and the ot
bÁTE .............
fAGE
EPROm addes eBoo0H)
6KX8
Rom
Ao-As Kom
(esen)
(odd)
o-s D,Ds
Pg-Ds
B2kx8. 32kXe
RAm
fodd (LO)
wR
RD CS
As?
Ars-A9 ’
DATE.......
PAGE
BHE Ao C S, CS
RAM BH& CSu
)
Cs, = Ct BHE
CS, = CtAo
=C't A
ohenesex a lange memsuy equned in aa
minoComputen sstem, the memoy suksyakem
Benay dstgned stng dyfomikam
asSdVasto -Adantseseqt hiqhen
packaginq donity , lowee castand es pouen
ons nptian
typal statie RAm cclt may Aaquke ir anistos
whilsthe dnamic RAmcell aeges nly a
tansisto along wth a capaciton.
tne, it. sd pomble to cbain highee packagins
densty and hense lovo cest enith ane vaiaste..
SOnLO Auioua dtaobak dy nami
Rni- The basii
dynonic
Stone the chaye
LATE ............
AGE
data as a diode
s capaitou
his monu<atvdthat
is -blastd tho stoase
that Aeerse
s
apacitnce Comes into the plcte
epsentation data
stouing cwet that
but t e s s e 1ased'diode
-
has
hao
tends to discharge
reakage
gksing ise to -the posih liy
hedataZafaitsu
loss. dala
thç pouiblo data loss, the
"to avold dunanle RAM cel must b
Stoued in a intenwal
feshed aftu a ixed tine the
ekulanly.
dta n the RAMu khounas
eadin
the data
hisactiuity #milae to eadi
indpenelet
Legiemer o miuopoocenas, segulanby
the ~euiod al othe ojsatia
Dusing thi ush
lasbd to th mamauy subsysttm esupendad
Hence the actitycauses los6of tinsy
suting n
Houieubl, keping ke low polse Consenptlo,
|dyhame RAm, Opi density and low cost, nnost
htgh po
athe tompikeu systm
sin dy namic RAny owrse at the cost
Oopedating sped.
utesh mechanism and the addito
Atho, the
jnanduau uq un ecd makas the intorcin
handware, in ca
DATE......../........
PAGE
conplicated as com paed to S tatii RAD
intongacinq cicut
A dedlcdted havdoe chip Called as dynomi
Am Cotolle íA the mast impodant past
of the intenyacng
om the
The
uead ycle,isi in difeusnt
Relresh cycte the
he mimay addesA not pcouled by
Hhe CPU ádless bs, atheu
mechanm cownte Kbu
Knoun ay
by aAfesh
eeteesh caunk.
Unltke memey Mead cyleyOe than One
memy chip y be anabled ata tine
edide the Ymbe 0 tota l
memouy
hedta 8n.tul
tnable -the selectd
memoy chipi deactivated, andl data fs not
aloutd to appea on the system data bus
moe thon one memo
nitsae efeeshed símtaneay.
Tnis is to avoid the clota om the aifeet
chips to appean n the bus muttaneDusy
ônitiated
14emouy eae is eithena pODCeAS0S
Dr anetenal bus masten iittatd oputen
Lohile mem at¯ted
uohile memoy cekeesth
nitaed
is an inclependt ogula
and Casled out 9y
Ocesh mechanisn
the
GATE ........
IAGE
enils ex0 eilobily to eoen mgabi
he
intsenally
memoy iss asangedaay Jo hat
too dimensional matbitk lamns
and Colun adden
The aclele n
mae in portart fos the
epation.
fouCamplaatypial 4* bit yndme
chiph n ntearallyangd
clmension 4X64je.69 ous
bt
hus the Ow addex amd column adaen
ejl eguice b bib cach
hee 6 bitykeu ach ow addneye anl colum
Cdees wiu be genatd
Counteu, dinq
A Complete Abw e ccells
at a'me to minimi 20 the seakceghing tm
-Thus,tha co lntr meedstogeita
ony ow aðtdOses.
The oLw adlsesses lee mutiplexed, Ouen
lowen rlen addoes lines
the uflsh Srals act to contuol ne
mttiptexen fed hen ufesth cucte in
pocess he Ayloh Ccunk.pu% the co
the addoeys bs
Dhuoise , the Cuadess bus o hepooa
DATE
PAGE
mouml poceo nitatd atiuitis
A
A imeu , called eesh ime, donts
Laleen ntutdl, hich Can be yuallath lL
delned tho ime kos tohlch a dinaic RAr
con hald data chage lesel pachically
c6nstant e no data lo%A toRos place.
Suppose the typical dyrannic RAM chip ho
ha
suos , theteach ots Should bes t t
ntealos in othe ody,
atlthe 64 oys asee to b Hefreshod Jn a
tis ikesh intewal aepends upon the
manu<acting techno logy cb the donamnic
Ramell
pulses wil be callubted as chon
3
64
32X )6 H2
Each o the ued chips is a l6X 1-bit dynami
The system contains too 6k
b byte dnomc
RAm enitA
tu the adayo and dota linas ae l&semad
to be
*o awailabo- Axsm an go8Gmicooconen
LATE . . . . . . . . . .
IAGE
System. lata
Te DE pin contols oeBput
E, the memeuy chips hign chiþdelecta
e,
The cs as& actie
pins
e memey chipa Sfant, ) the feth
ne seefreh cycle qBLs high,
th ufeh imen.
tpct Qlso
the nestory Chip.
The high CE enablesnigh 0 pulenta
on efeshiny ohile n-the dat bus
Ppeann
assid
said in the cescu~tion % thu mom
lesh cyde
|-bit cymic RAM has an
|6K
ntcuna toddOes, The loe
bit pr
Delen lins Ao -Az ave mutiplxad
wj th tho efesh cauntr output Ao -A
bATE ..!
PAGE
16kx
ogi
Rebeshing 6X1
16kX
RAm
Doríding
Dymamic
Pb-Ais
As
Ps
DArE ........
PAGE
# Read /wsite Timing Oiagom -
AU
) minimem Mes at loast y-7
ot nt
C cle
s qisen
T.The dddes
States (,, TE, Ta, T, state . gt ú diaila
he
Dy pocessOr in Tstate
o one
on the bus tistated ot changing
Tn Tay, the buis Noad cicl.
bs! in case o
the diLectibn o! uTTy
place
he data tans7u takes
4 addresed denice i then coait
sloua0
slouset
sYate anol Ty
insexted bw Ta lndl
MemBiy ReadCycleTining Dägxam.
ALE
Addlsohuy BHE S- `3
Bus sed
A8d/Dato As-Ab Ds-D,
Rp'
DEN
DATE ... ........
fAGE
NemeAy Rcad aycle
Dwing poccod T, :
CBat ALE =Ly this îndicates that a vaid
address latch ed on the cuddses bus and
m)TO=, ohich [ncatca the memoy
poge
Dweing peiod Ta:
The atldes s HemOUed tom the locat b
nd s Set to the adotoed deice
LDnen RO0,te nlid decta is peent n
the cata bu
Aso , uin T, De) =0, shich enebles
TRansceies and
and orR
0TR -0,ohich indicates
Ahat tha datau uuceied
Dusing, T3:put
Data on the data bs and the
The otpt dcsice mabs the £eADY Une hb
hiA mans the Ottpt cleuie hes peomed
makes the uead sianal to then the 0utpc
desice wl again tustate ta bus dyjsees.
PAGE
Nemsy korite leycle
B7E, P9-Ab
Valid s-Do
DEN
AT T , State ALEl, thís indicatey tot
valid adduexo ís latched on the adoes
bus cnd also m)ToL, ohich îndiates
he memy opoiation s in puoges.
Sh Tz, the pOCeKSO send the olata to
be siten t the addscessed lacation.
The d ata is bulhered on the bw ntil
the mfddle c ty State
bec6mes o at he
The wR begiring Ta
bATE
PAGE
he Bltg and Ao sgnals ase e od oselet:
he bye bytei
Ta DTNO, ohich enables toane
and p1)K=L ohich jndícaty thct
data. is ansfead by th e Procorsae
addessed deuia.
Clock
AD-Aas H
Be/ S
2236
-luit
data
TNTR anseEta
DTIR Dus
74138
384.
Date
(agica)
tR
lamseot
bus)
DATE
PAGE
Maximum Node 3
Waite option Timing agom
T3
ALE
Actiue
TroctiueX Aciue
S-Sa
Ars-t, Dota out
Dota bDo
high
DTIR
DeN
’ Rcad operation Timing DiagonI
GATE ./. /..
PAGE
CLk
Actie KInectiueX Actiue
deita
DTIE
DEN
thestates snala So ,S, S ot theuntit
snal
Pegnning% bd cycle beomes actie
whn So = S)= S,) 8288 bs canbolles
usiu output a puse.
aqisad sgnal
Tn Ta,R8 toi l set PEN=enabling toensceias
and mkDc and ILORC ae qctivctedThex
e aciuated entil Ly foDGn Qutp the Amc
DAE
PAGE
oll onain
The Sttus bis Sa to S,
actiue til T3
cady input u not achiuated bfore
T3 loitState
and,
>CK Si 9288
READ B0S
ocnetor CTRLR
DEN
CPU Ackroalc
L0CK kNc
wait
State
Geneotor
|INegabyt
g282
AD-AD's (2oR3 )
Pl-ig
6-Bet
Datd
(2)
Marimurn Made
