(e) F(4,B,C,D)- X

1,2.4,5, 7,8, 10,1 I,13,14

() F{4,B, C,D)-X0,5,7,8,9,10,11,13
3-10. Simpl1ly the following using u K-map:
(a) {A, B,C, D) =S0,2,3,5,7,8, 12,13
(b) F{A,B, C,D) =2I,3,4,5,6,11,13,14,15
(c) FA,B. C,D)=L,2,4,5,6,7, 12, 15
(d) \A, B.C,D)= X0,4,5,8,9,10, 13,14,15
(e) F(4,B, C,D) - X0,2,3,4,5,|1,13,14,15
3-11. Simp1fy the following:
(a) FA,B.C,D, E)= 0,4,8,12, l6,20,24,28
(b) F(A, B. C,D, E)- X0,2,5, 10,13, 15,16,20,21,26,27,31
(c) F(A,B. C,D, E) =0,2,5,8,13,1S,18,21,24,29,3|
(d) F(4,B,.C,D, E)=X8,9, 10,11,13,15, 16, 18,21,24,25,26,27
(e) F(A, B, C,D. E)= S0,4,5,6,7,l1,12,13, 14,15,21,23,27,28,29,30,31
() F(A, B, C, D, E)= S1,2,3,4,5,7,8, 10, 12,15, 16,18,19,21,22,23,24,26,27,31
3-12. Simplify the following:
(a) FA,B, C,D,E, F)=>6,9, 13, 18, 19,25,27,29,4 1,45,57,61
(b) F(A,B,C, D, E, F) =)4,5,6,7, 8,9,14,2 1,23,29,3 1,37,38,39,45,47,49,51,52,53,55
(c) F(A,B,C,D, E, F)=0,1,5,6,9,15, 16,18,21,25,29,30,35,37,39,40,45,48,49,50,55.58.
60,61,63
(d) F(A, B, C, D, E, F)=24,5,6,7,8,18,20,23,25,26,27,28,37,38,42,44,49,5 1,58,59,60,63
(e) F(4,B, C,D, E, F)=20,1,2,3,9,10,11,14,15,20,23,24,26,27,29,30,31,33,36,41,42,47,
48,49,52,58,59,62,63
3-13. Find the set of ALL prime implicants, then identify the essential, necessary.
optional, and redundant implicants in this set for the following:
(a) Problem 3-8
(b) Problem 3-10
(c) Problem 3-11
(d) Problem 3-12
3-14. "Don't care" problems. Simplify:
(a) F(A,B,C,D) = 21,3,5,8,9, 11, 15,9,(2, 13)
(b) F(4,B,C,D) = 24,5,7, 12, 14,15, 9.(3,8,10)
(c) F(A,B, C,D)= 20,4,5,6,7, 0, (12, 14)
(d) F(4,B,C,D) = E3,7,8, 12, 13, 15,9, (9,14)
(e) F(A,B, C,D)=E4,5,6, 12, 13, 9,(2,9, 15)
() F(AB, C,D, E, F) =E5,7, 13, 15,19,27,28,29,30,3 1,32,37,39,45,47,51,53,55,61.65,
9, (2,8,10, I6,26,40,41,42,43,56,57,58,59)
3-15. Reduce the following using the single statement reduction criteria:
(a) Problem 3-8
(b) Problem 3-9
(c) Problem 3-1|
(d) Problem 3-12
3-16. Simplify the following using a K-map:
(a) F(4,B, C,D, E)= CDE +ABCE + ABDE +ABCE
(b) F(A,B, C,D, E) =ABCE +BDE+ BCDE+ ABDE
(c) F(A,B, C,D, E)=ABC + BCD+ BE+ CE
(d) F(A,B, C, D, E)=ABC +ADE+ CDE+ BC

188 Minimization and Design of Combinational Circuits

 (e) F(4,B, C,D, E, F)- ABCDE + ACD+ WIDE +AhCD+ABEF
3-17. Using the expressions of Problem 34, plot maps and reduce
3-18. Using the expressions of Problem 3-5, plot maps and reduce.
3-19. Find the simplified POS expressions for Problern 3-7 and conpare with SOP form
3-20. Find the simplified POS expressions for Problem 3-8 and cormpare with SOP form.
3-21. Find the simplified POS expressivns for Problern 3-9 and compare w1th SOP form.
3-22. Find the simplified POSexpressions for Problem3-14 and compare with SOP furm.
3-23. Find the minimal cover for the following multiple-output problems:
(a) Fi(A, B, C, D)=1,12,13, 14, 15
Fz(4,B,C,D) = E3,7,1 1, 12,13,15
F;(4,B, C,D) = 23,7, 12, 13, 15
(b) F(A, B, C,D ) = $2,3,5, 7,8,9, 10,1 1,13,15
F(4,B,C,D) = )2,3,5,6,7, 10,11,14,15
Fs(A,B, C,D)= E6,7,8,9, 13, 14, 15
3-24. Simplify using twØ-variable VEM for each of the output functions:
A B
0 1

0
0
1 0
1 0

0 0

two-vanable
SimplifyF,, F, and, using a three variable VEM. Simplify F using a
35.
VEM at your own risk.
A B D F, F
0
0
0
0
0
2
3 0
1
4
5 (0
6 0
7

0 0
0
10 0

12
0
13
14

Problems and Exerc1ses 189

3-26. Using the MEV echnique, simplify the exercises set forth in
three-varnable maps. Problern 3-10
wang
3-27. Simplify , and F, using a four-variable VEM.

A B D
F,
)

1
0 0
0
0

1 1 1
1 0
1

0 0 0
1 0

0
1
1 1

3-J| usng
3-28. Using the MEV technique, simplify the exercise set forth in Problem
four-variable maps. 3-16using
3-29, Using the MEV technique, simplify the expression Problem
Set forth in
four-variable maps.
3-30. Write the simplified expressions for the maps in Figure P3-.
3-31. Write thesimplified expressions for the maps in Figuré P3-2.

190 Minimization and Design of Combin

 AB
C 00 01 11 10 00 01

D DO DO 1

1 D)

Flgure P3-I

AB AB
CO 00 01 11 10 CD 00 01 10
12

00 1 00 1

01 Y 01

11 y 1 1 11F FO FO FO

10

10 YO YO 10 1 FO

Figure P3-2

3-32. Using MEV techniques, simplify the following expressions:

(a) F(A,B, C,D, W,X, Y,Z)= ABCD+ ABCD(X) +ABCD(Z+ W)+ABDNL
+ ABCDX)+ ABCDI(X + Y)Z]+ ABCD(Z Y)
+ ABCD W)+ ABCD+ ABCD Xø}W+YWAB+ X Y}W
(b) F(A, B, C,D, W,X, Y,Z)= XYZWA +
+XYZWIA +B)C) +XYZW+ XYZW(C+ D)+XøZW(DOB)
.AB(DQR
(c) F(A,B, C,D, 0,R,S, T) = ABCD(R+ S)+ ABCD + ABCD +
+ABCD + ABCDO+T) +A BCDST+ ABCD + ABCD +AB(DE
(d) F(A, B, C, D, E, F,G, H, K) = ABCDE+ ABCDE(F Ð K) + ABCDE
+ABCDEFGH + +ABCDEFG + ABCDE[ G(F+ K)) +4BCDEHF
ABCDEG t A BCDE
+ ABCDEHK+ ABCDE + ABCDEF+
3-33. Given the following four-variable map (Figure P3-3):
VEM and reduce it.
(4) Compress this map into a three-variable
(wo-variable VEM. then reduce
(b) Compress the three-variable map done into a
this function. Check your results.
Note: Problems 3-34 through 3-38 are special implementation problems given for you to
logIe
practice drawing neat and well-documented schematic diagrams using mixed
prercuuisile
and polarized mnemonic notation. These are considered an inmportant
to the rest of the problem set.

Problems and ExerCIses 191

3-38. Implement the following control equations minimizing the use of inverters. Show
in1plementations in full polarized mnemonic notation. You can use:
(a) two- and thrce-input AND gates
(b) two-input OR gates
(c) two0-, three-, four-, and cight-input NAND gates
(d) (w0- and three-input NOR gates
Inputs: A, B, C, D, 10g, and 5g are double rail input
Inputs: NICKEL, DIME, QURTR, CR, COIN are single rail ASSERT ED HIGH
(a) F=ABD + BCD + BC(DIME)+ ABD(10g+5)
(b) F= ABCD + ABCD(NICKEL)+ ABD(5g +10) + ABDI0z +5g)
+ BACD(CR) + ABC(CR)
(c) F= ABD + CD+ BCD(COIN) + AD (10e+ 5e)+ BCD(5E)
(d) F BCD + BCD(DIME) + BD(Sg+ 10z) + AC
(e) F= AB + A(5e+ 10c) + B(10e + 5c) + ABD(QURTR)
Note: The following problems are a selection of combinational design exercises. It is
intended that the full design prOcess be carried out including fully documented
schematics done in mixed logic format.
Design a combinational circuit with four inputs (4,B,C,D) and one output (). The
output will be ASSERTED when the following conditions prcvail: (1) all inputs
are ASSERTED: (2) none of the inputs are ASSERTED; (3) an odd number of
inputs are ASSERTED.
Obtain the TRUTH-TABLE.
Find the output function in SOP.
y Find the output function in POS. HIGH and LOW Use
) Draw logic diagrams for both functions ASSERTED
mixed logic format. Minimize your use of lNVERTERS. LOW. Assume inputs A and
are ASSERTED
B are ASSERTED HIGH and C and D
number with Z representing
Use the variables W, X, and Y to represent a three-d1g1t
the number is positive: if z is
the sign of the number. If Z is ASSERTED, that the followin
NOT-ASSERTED, the number is negative. Design a circuit such
specifications are met.
output equals that number minus two.
When the number is negative, the
output equals that number plus two.
When the number is positive, the realization
Obtain the TRUTH-TABLE; plot maps for SOP and POS
(a)
diagram using mixed logiC with output ASSERTED HIGH , .d
(b) Draw the logic ASsume all nputs are ASSERTED
LOW Minimize your use of INVERTERS.
LOW. outnut os.
three-digit binary number, des1gn a Circuit that generales an
With a
of that number.
equalto thesquareTRUTH-TABLE.
(a) Define the POS.
Show allmaps for SOP and output ASSERTED HIGH,
(b) logic diagram with HIGH minimizing use of
Draw the ASSERTED
(c)
INVERTERS. Assume all inputs are
A(H),
combinational system with inputs be B(L), and C(H) and (wo outputs
to
3-42. Design a
= I(L), where- x and y are he interpreted as the binary number
X=I(H and y represent decimal value of the number of
This number (xy) is to
(xy). at any time.
present
ASSERTED inputs
Problems and Exercises 193
 347. For thc LED seven sepment display treated in
Ptoblem 346, re
decoder such that any lime acode outside the range of (MO to 1(deugn the ply
letter E is displayed indicaling Eror. Assume BCD inputs are preent the
ASSERED LOW
Carry out the complete process includ1ng schematics draw1ngs in mixed loge and
polarizcd mnemonic notation.
348. For the LEDseven scgnent display shuwn in Problem 3-46, des1gn a decoader ihat
will perform according to the following speificatons. Assume B ) inputs re
ASSERTED LOW. Carry out the complete design process including schernatic
drawings in mixed logic and polarized mnemonic notat1on.
A B D SevenSegment Output

0
2

0
0 6

1 7

9
A
B= lower case b
0 C
D=lower cased D
E
F

the XS-3 code

two-level combinational system that converts involv1ng 9
349. Design a minimal cover multi-function minimization
problem
this is a complete
to NBCD. Note that outputs ASSERTED HIGH.) Carry out themnemonic
entries. (AII inputs andschematic drawings in mixed logic and polarized
design process including
five inputs.
notation.
two-level combinational system that has
cover
3-50. Design a minimal ASSERTED as follows:
SABCD, which are bit
S= +(H) sign
A =l(L) (MSB)
B= I(L)
C= I(L)
D= l(L) (LSB)
convert
binary number and in turn
signed out the
decode these inputs as a ASSERTED LOW, (arrypolar1zed
to
TOur system iscomplement. Outputs are to bedrawings n mixed logic and
it to its 2's
process including schematic
cOmplete design alarm that is
reyuired
mnemonic notation. the seat belt to the
to implement
be designed switches is available t0 supply the inputs
network is to neutral). A
3-51. A logic sensor engaged (not in
cars. A set of the gear shift is
On all new switch wil be turned on if each willturn onif someone will turn
sits in the
network. One front seat and seat which
under each attached to each front
SWitch is placed Fin:lly, a switch
is
corresponding seat. Problems and Exerc1ses 195