Jayawant Shikshan Prasarak Mandal’s

Rajarshi Shahu College of Engineering,

Polytechnic.
Academic Year: 2023-24
CLASS: EJ-3I
SUBJECT: Digital Techniques (22320)

A MICRO-PROJECT REPORT
ON
“Design Full Adder using Boolean Expressions”

SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE AWARD OF DIPLOMA IN
ELECTRONICS AND TELE-COMMUNICATIONS DEPARTMENT

SUBMITTED TO
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION,
MUMBAI

SUBMITTED BY

Name of Students Roll No’s.

1. Aryan Aich SYEJ51

2. Aditya Doke SYEJ52

3. Pavitra Neelannavar SYEJ53

GUIDED BY
Mrs. M. A. Patil Mhaske
 Maharashtra State
Board of Technical Education, Mumbai
(Autonomous) (ISO-9001-2008) (ISO/IEC 27001:2013)
CERTIFICATE

This is to certify that Mr.,

1. Aryan Aich
2. Aditya Doke
3. Pavitra Neelannavar

of Third Semester of Diploma in Electronics and Telecommunication Engineering of

Institute, JSPM’s Rajarshi Shahu College of Engineering Polytechnic (Code: 1620) have
completed the Micro-project satisfactorily in course Digital Techniques (22320) for the
Academic Year 2023 to 2024 as prescribed in the curriculum.

Place: Tathawade, Pune Enrollment No’s: 1. 2216200426

2. 2216200427

Date: ______________ 3. 2216200428

Mrs. M. A. Patil Mhaske Mrs. A. N. Dubey

(Course Incharge) (Head of Department)
 CONTENTS

ACKNOWLEDGEMENT............................................................................................................. ii
ABSTRACT ............................................................................................................................. iii
I. Introduction: ...................................................................................................................1
II. Theoretical Background: ..................................................................................................2
III. Block Diagram of Full Adder: ............................................................................................3
IV. Truth Table of a Full Adder: ..............................................................................................3
V. How Sum and Carry is obtained: ......................................................................................3
VI. K-Map Simplification:.......................................................................................................4
VII. Boolean Expressions: .......................................................................................................4
VIII. Full Adder Circuit Design: .................................................................................................5
IX. Experimental Setup:.........................................................................................................5
X. Operational Details: .........................................................................................................6
XI. Resources / Components Used: ........................................................................................7
XII. Precautions followed: ......................................................................................................7
XIII. Observations for the Setup used: .....................................................................................8
XIV. Results:............................................................................................................................8
XV. Conclusions: ....................................................................................................................8
XVI. Advantages of Full Adder: ................................................................................................9
XVII. Applications of Full Adder: ........................................................................................9
XVIII. References: ...............................................................................................................9

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JSPM’s RSCOE Polytechnic | E&TC Department
 ACKNOWLEDGEMENT

I would like to extend my heartfelt gratitude to all those who contributed to the successful
completion of our micro-project at JSPM’s RSCOE Polytechnic.

First and foremost, I would like to express my deepest appreciation to our project
advisor, Mrs. M. A. Patil Mhaske, for their invaluable guidance, unwavering support, and expert
insights throughout the project, as well as our Principal Prof. Sarita. S. Gaikwad for providing us
the opportunity to build and research on this project. I would also like to thank our dedicated
team members for their hard work and commitment to this project.

Lastly, a special thanks to our families for their constant encouragement and
understanding during this endeavor.

Date: ___________________ Aryan Aich (SYEJ 51)

Place: ___________________ EJ-3I

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JSPM’s RSCOE Polytechnic | E&TC Department
 ABSTRACT

The "Full Adder" project presents a comprehensive exploration and implementation of a

fundamental component in digital circuitry. A full adder is a crucial building block for binary

arithmetic operations, essential in the design of various digital systems, including processors and

integrated circuits. This project delves into the theoretical foundations of binary addition,

detailing the operation of a full adder circuit. The study encompasses the logic design, truth

tables, and mathematical formulations governing the sum and carry-out computations.

The practical aspect of the project involves the hands-on construction of a full adder circuit using

logic gates, such as XOR, AND, and OR gates. The project explores the interplay of these gates

to achieve efficient and accurate binary addition. Additionally, considerations for carry

propagation across multiple bits are addressed, highlighting the significance of full adders in

multi-bit arithmetic.

Furthermore, the project investigates potential applications of full adders in digital systems,

emphasizing their role in arithmetic logic units (ALUs) and other computational modules. The

outcomes of this project contribute to a deeper understanding of digital circuit design principles

and lay the groundwork for more complex arithmetic operations within digital electronics.

In conclusion, the "Full Adder" project serves as a valuable resource for students, researchers,

and enthusiasts in the field of digital electronics, offering insights into both the theoretical

underpinnings and practical implementation of this foundational component in binary arithmetic

circuits.

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JSPM’s RSCOE Polytechnic | E&TC Department
 Design Full Adder using Boolean Expressions

I. Introduction:

In the realm of digital circuit design, the creation of robust and efficient adder circuits is
fundamental to the development of complex computational systems. One such essential
component is the Full Adder, a building block that plays a pivotal role in arithmetic operations
within digital circuits. This project delves into the design and implementation of a Full Adder
using Boolean expressions, offering a comprehensive exploration of the underlying principles
and logical constructs.

A Full Adder is a crucial element in binary addition, capable of summing three input bits
and generating both a sum and a carry-out. By leveraging Boolean expressions, which
encapsulate the logical relationships between input and output bits, we aim to construct a
versatile and efficient Full Adder circuit. This project not only focuses on the theoretical aspects
of Boolean algebra but also provides a practical hands-on approach to building and testing the
Full Adder circuit.

Throughout this exploration, we will navigate the intricacies of Boolean logic, unveiling
the foundational principles that govern the behavior of digital circuits. The project will guide you
through the step-by-step process of deriving Boolean expressions for the sum and carry-out
functions of a Full Adder, emphasizing clarity and understanding.

By the end of this endeavor, you will have a solid grasp of how Boolean expressions can be
translated into functional circuits, with the Full Adder serving as a tangible example. This project
not only enriches your understanding of digital design but also equips you with the skills to
implement Boolean expressions in practical circuitry, laying the groundwork for more advanced
studies in digital electronics. Join us on this journey as we unravel the intricacies of Full Adder
design using the powerful language of Boolean expressions.

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JSPM’s RSCOE Polytechnic | E&TC Department
 Design Full Adder using Boolean Expressions

II. Theoretical Background:

A Full Adder is a fundamental building block in digital circuit design, particularly in the
realm of binary arithmetic. It is used to add two binary numbers, taking into account not only the
sum of the individual bits but also the carry from the previous stage. A full adder has three inputs
- A, B, and a carry input (Cin) - and two outputs - the sum (S) and the carry out (Cout).

The core functionality of a full adder

involves the addition of the three inputs: A, B,
and Cin. The sum output, S, is the result of the
modulo-2 addition of the inputs, representing the
least significant bit of the sum. The carry out,
Cout, signifies whether there is a carry-over to
the next higher bit. In essence, a full adder
Figure 1: Block Adder of Full Adder
encapsulates the carry propagation mechanism
essential for multi-bit addition.

The truth table for a full adder exhaustively outlines all possible combinations of inputs (A,
B, Cin) and the corresponding outputs (S, Cout). The logic gates within a full adder circuit,
typically implemented using XOR, AND, and OR gates, work together to produce the correct
sum and carry outputs.

Full adders are crucial components in the design of arithmetic logic units (ALUs) and are
extensively used in microprocessors, digital signal processors, and other digital integrated
circuits. By cascading multiple full adders together, it is possible to create more complex
arithmetic circuits capable of adding multi-bit binary numbers. The efficiency and reliability of
full adders play a pivotal role in the overall performance of digital systems, making them
indispensable in the field of digital electronics.

Over the next pages, this Report further discusses the designing of a Full Adder using
Boolean Expressions, K-Map Simplification and finally designing of the Full Adder using the
Expressions obtain from K-Map Simplification.

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 Design Full Adder using Boolean Expressions

III. Block Diagram of Full Adder:

Figure 2: Full Adder in a Block Illustration.

IV. Truth Table of a Full Adder:

Input Output
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

V. How Sum and Carry is obtained:

The way Sum and Carry are generated is pretty simple. Firstly, a normal Binary
Addition is applied to the Inputs (A, B, Cin). According to the result of the addition,
Sum and Carry is generated.
For example, adding 0, 1, 1 produces a Sum 0, but produces a Carry 1. Similarly,
adding 1, 1, 1 produces a Sum 1, as well as a Carry 1.
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 Design Full Adder using Boolean Expressions

VI. K-Map Simplification:

1. K-Map for Sum:

A / BCin B Cin B Cin B Cin B Cin

A 0 1 0 1
0 1 3 2

A 1 0 1 0
4 5 7 6

2. K-Map for Carry:

A / BCin B Cin B Cin B Cin B Cin

A 0 0 1 0
0 1 3 2

A 0 1 1 1
4 5 7 6

VII. Boolean Expressions:

Note: For variables with value 0, they are represented in Complemented Form.
For variables which have the value 1, they are represented in Normal or Un-complemented
form.

1. From the given Truth Table, we obtain the following Boolean Expressions for Sum:

• Sum = A B Cin + A B Cin + ABCin + ABCin

• ∴ Sum = A ⊕ B ⊕ Cin

For realizing the expression of Sum, an EX-OR gate will require, with 3 inputs.

2. From the Given Truth Table, we obtain the following Boolean Expressions for Carry
(Cout):

• Cout = ACin + BCin + AB

• ∴ Cout = AB + BCin + ACin

For realizing the expression of Carry, Three AND gates will be required, whose outputs are
combined using One OR gate with 3 inputs.

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 Design Full Adder using Boolean Expressions

VIII. Full Adder Circuit Design:

Figure 3: Practical Circuit Diagram.

IX. Experimental Setup:

Figure 4: Actual Circuitry of the Project.

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 Design Full Adder using Boolean Expressions

X. Operational Details:
The operation of a full adder can be understood by examining its internal logic and how it
processes input signals to produce output sums and carries. Let's break down the operation step
by step:

Inputs:
A, B: The two binary digits to be added.
Cin (Carry In): The carry input from the previous stage or bit.

Sum (S) Calculation:

The sum output, S, is calculated using an XOR (exclusive OR) gate. The XOR gate takes inputs
A, B, and Cin. The output of the XOR gate represents the modulo-2 addition of the inputs.
The sum bit (S) is the least significant bit of the addition and is given by S = A ⊕ B ⊕ Cin.

Carry Out (Cout) Calculation:

The carry output, Cout, is determined by two AND gates and an OR gate. The AND gates take
different combinations of A, B, and Cin as inputs.
The first AND gate considers A and B, producing a partial product.
The second AND gate takes the output of the first AND gate and combines it with the logical OR
of A and B, producing another partial product.
The OR gate combines the outputs of the two AND gates, and the result is the carry-out bit
(Cout).

.
Mathematically, Cout = (A B) + (B . Cin) + (A . Cin).
Output:
The full adder outputs two values: the sum (S) and the carry-out (Cout). These outputs can be
used as inputs for the next stage in a multi-bit addition.
In summary, a full adder performs the addition of three binary bits (A, B, Cin) and generates two
outputs: the sum (S) and the carry-out (Cout). It combines XOR, AND, and OR gates to achieve
this, making it an essential building block for designing circuits that perform binary addition in a
cascaded manner for multi-bit operations.

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JSPM’s RSCOE Polytechnic | E&TC Department
 Design Full Adder using Boolean Expressions

XI. Resources / Components Used:

Sr.
Name of Resources Specifications Quantity
No.

Digital Multimeter: 3 ½ Digit

1. Multimeter 1
Display

2. IC Tester Digital IC Tester 1

3. Breadboard 5.5cm x 17cm 1

9V; 1500mAh Capacity; Carbon-

4. Battery 1
Zinc.

5. Logic Gate ICs IC Numbers – 7408, 7486, 7432 1 each.

White; 5mm; Forward Voltage – 25cm each

6. LEDs
2.5V. color.

Single strand, 0.6mm inner dia,

10cm each
7. Connecting Wires Teflon Coated; Colors used - Red,
color.
Black, Yellow, Green, Purple.

1/8th Watt (0.25W); 330Ohm, 2 qty. each

8. Resistors
220Ohm, 100Ohm value.

9. Zero PCB 10cm Length, 5cm Breadth 1

10. IC Base 14 pin DIP; 18x10x4mm 3

XII. Precautions followed:

1. 9V Battery’s Cap was always removed, incase wires short-circuit and the Battery drains
out.
2. Experimental Setup was kept and transported with care.
3. While performing the practical, a non-ESD, non-Conductive surface was kept underneath
the setup to prevent any electrical faults.
4. Soldering process was done under a guardian’s supervision to prevent accidents and get
proper guidance and instructions for performing the process properly.
5. The soldering iron was not kept for too long over any terminal pins, to prevent overheating
issues due to which damage might have occurred.

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 Design Full Adder using Boolean Expressions

XIII. Observations for the Setup used:

Input Output
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

XIV. Results:
1. When inputs – (0, 0, 1); (0, 1, 0); (1, 0, 0); (1, 1, 1) are applied to the Full Adder setup, only
then the Sum Output becomes High. At rest of the inputs, Sum stays Low.
2. When inputs (0, 1, 1); (1, 0, 1); (1, 1, 0); (1, 1, 1) are applied to the Full Adder setup, only
then the Carry Output becomes High. At rest of the inputs, Carry stays Low.
3. Ultimately, when all Inputs (A, B, C) are High, both the Outputs (Sum, Carry) become
High.

XV. Conclusions:
Full Adder is a combinational circuit, consisting of simple gates like AND, OR and EX-OR
which has a special functionality of adding 3 binary digits.

The circuit we constructed is a Full Adder. This circuit under rigorous testing came out to
be OK. The circuit produces appropriate outputs for each input combination.

Thus, the circuit is ready for demonstration, use, and submission.

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 Design Full Adder using Boolean Expressions

XVI. Advantages of Full Adder:

1. Full Adder provides facility to add the Carry from the Previous Stage.
2. The power consumed by the Full Adder is relatively less as compared to Half Adder.
3. Full Adder can be easily converted into a Half Subtractor just by adding a NOT gate in the
circuit.
4. Full Adder produces higher output that Half Adder.
5. Full Adder is one of the essential parts of critical Digital Circuits like Multiplexers.
6. Full Adder performs operation at Higher Speed.

XVII. Applications of Full Adder:

1. Full adders are used in ALUs (Arithmetic Logic Units) of CPUs of Computers.
2. Calculators.
3. Carrying out Multiplication of Binary Numbers.
4. To realize critical Digital Circuits like Multiplexers.
5. To generate Memory Addresses.
6. Generation of Program Counterpoints.
7. GPUs (Graphical Processing Units).

XVIII. References:
[1] "Full Adder in Logic Circuits". www.geeksforgeeks.org.

[2] Omar Muñoz Urias (27th Oct 2022). "Full Adder Circuit - How it Works". www.build-

electronic-circuits.com.

[3] "Full Adder". www.javatpoint.com.

[4] Credits to Google Images for Pinout Diagrams of various trivial components.

[5] Credits to Wikipedia for small snippets of information about all the components.

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JSPM’s RSCOE Polytechnic | E&TC Department