Lecture 9

Synchronous Sequential Circuits - II

Prabha Sundaravadivel
Assistant Professor
Department of Electrical Engineering
The University of Texas at Tyler
3900 University Blvd. RBN 1008,
Tyler, TX. 75799
Email: [email protected]

Module 9
EENG VLSI 4332, 5335
Week 13

Week 13 Synchronous Sequential Circuits II Slide1

 Design steps:

1. Obtain the specification of the desired circuit.

2. Derive a state diagram.
3. Derive the corresponding state table.
4. Reduce the number of states if possible.
5. Decide on the number of state variables.
6. Choose the type of flip-flops to be used.
7. Derive the logic expressions needed to implement the
circuit.

Week 13 Synchronous Sequential Circuits II Slide2

 Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0

Figure 6.22. Sequences of input and output signals.

Week 13 Synchronous Sequential Circuits II Slide3

 Reset
w = 1 z = 0

w = 0 z = 0 A B w = 1 z = 1

w = 0 z = 0

Figure 6.23. State diagram of an FSM that realizes the task in

Figure 6.22.
Week 13 Synchronous Sequential Circuits II Slide4
 Present Next state Output z
state w= 0 w= 1 w= 0 w= 1
A A B 0 0
B A B 0 1

Figure 6.24. State table for the FSM in Figure 6.23.

Week 13 Synchronous Sequential Circuits II Slide5

 Present Next state Output
state w= 0 w= 1 w= 0 w= 1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1

Figure 6.25. State-assigned table for the FSM in Figure 6.24.

Week 13 Synchronous Sequential Circuits II Slide6

 z

w D Q
y

Clock Q

Resetn

(a) Circuit

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1
Clock
0
1
w
0
1
y
0
1
z
0

(b) Timing diagram

Figure 6.26. Implementation of FSM in Figure 6.25.
Week 13 Synchronous Sequential Circuits II Slide7
 Figure 6.27. Circuit that implements the specification in Figure 6.2.

Week 13 Synchronous Sequential Circuits II Slide8

 w = 0

A Reset

w = 1  R 2out = 1, R 3in = 1

w = 0 R 1out = 1, R 2in = 1
w = 1

w = 0 R3 = 1, R1 = 1, Done = 1
w = 1 out in

Figure 6.28. State diagram for Example 6.4.

Week 13 Synchronous Sequential Circuits II Slide9
 module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuit

always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
elsey <= Y;

// Define output
assign z = (y = = C);

endmodule Figure 6.29. Verilog code for the FSM in Figure 6.3.

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 module mealy (Clock, Resetn, w, z); B: if (w)
input Clock, Resetn, w; begin
output reg z; z = 1;
reg y, Y; Y = B;
parameter A = 1’b0, B = 1’b1; end
else
// Define the next state and output begin
combinational circuits z = 0;
always @(w, y) Y = A;
case (y) end
A: if (w) endcase
begin
z = 0; // Define the sequential block
Y = B; always @(negedge Resetn, posedge Clock)
end if (Resetn = = 0) y <= A;
else else y <= Y;
begin
z = 0; endmodule
Y = A;
end

Figure 6.36. Verilog code for the Mealy machine of Figure 6.23.

Week 13 Synchronous Sequential Circuits II Slide11

 Figure 6.37. Simulation results for the Mealy machine.

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 Figure 6.38. Potential problem with asynchronous inputs to a Mealy FSM.

Week 13 Synchronous Sequential Circuits II Slide13

 A

a
Shift register
s
Adder
FSM Shift register
Shift register
b
Sum = A + B
B
Clock

Figure 6.39. Block diagram for the serial adder.

Week 13 Synchronous Sequential Circuits II Slide14

 Reset ab  s 
11  0

00  0 01  0
01  1 G H 10  0
10  1 11  1

00  1

G: carry-in = 0
H: carry-in = 1

Figure 6.40. State diagram for the serial adder FSM.

Week 13 Synchronous Sequential Circuits II Slide15

 Present Next state Output s
state ab =00 01 10 11 00 01 10 11
G G G G H 0 1 1 0
H G H H H 1 0 0 1

Figure 6.41. State table for the serial adder FSM.

Week 13 Synchronous Sequential Circuits II Slide16

 Next state Output
Present
state ab =00 01 10 11 00 01 10 11
y Y s
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

Figure 6.42. State-assigned table for Figure 6.41.

Week 13 Synchronous Sequential Circuits II Slide17

 a s
Full
b
adder Y y
D Q
carry-out

Clock Q

Reset

Figure 6.43. Circuit for the adder FSM in Figure 6.39.

Week 13 Synchronous Sequential Circuits II Slide18

 Reset

11 01
00 G 0 s = 0 H0 s = 0
10

00
01 00 11 01
10 11 10

01 G 1 s = 1 H1 s = 1 11
10 00

Figure 6.44. State diagram for the Moore-type serial adder FSM.
Week 13 Synchronous Sequential Circuits II Slide19
 Present Nextstate Output
state ab =00 01 10 11 s
G0 G0 G1 G1 H0 0
G1 G0 G1 G1 H0 1
H0 G1 H0 H0 H1 0
H1 G1 H0 H0 H1 1

Figure 6.45. State table for the Moore-type serial adder FSM.

Week 13 Synchronous Sequential Circuits II Slide20

 Nextstate
Present
state ab =00 01 10 11 Output
y2 y1 s
Y2 Y1
00 00 01 01 10 0
01 00 01 01 10 1
10 01 10 10 11 0
11 01 10 10 11 1

Figure 6.46. State-assigned table for Figure 6.45.

Week 13 Synchronous Sequential Circuits II Slide21

 Sum bit Y1 y1
a D Q s
Full
b
adder Carry-out
Q

Y2 y2
D Q

Clock Q

Reset

Figure 6.47. Circuit for the Moore-type serial adder FSM.

Week 13 Synchronous Sequential Circuits II Slide22
 module shiftrne (R, L, E, w, Clock, Q);
parameter n = 8;
input [n-1:0] R;
input L, E, w, Clock;
output reg [n-1:0] Q;
integer k;

always @(posedge Clock)

if (L)
Q <= R;
else if (E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;
end

endmodule

Figure 6.48. Code for a left-to-right shift register with an enable input.

Week 13 Synchronous Sequential Circuits II Slide23

 module serial_adder (A, B, Reset, Clock, Sum);
input [7:0] A, B;
input Reset, Clock;
output wire [7:0] Sum;
reg [3:0] Count;
reg s, y, Y;
wire [7:0] QA, QB;
wire Run;
parameter G = 1’b0, H = 1’b1;

shiftrne shift_A (A, Reset, 1’b1, 1’b0, Clock, QA);

shiftrne shift_B (B, Reset, 1’b1, 1’b0, Clock, QB);
shiftrne shift_Sum (8’b0, Reset, Run, s, Clock,
Sum);

// Adder FSM
// Output and next state combinational circuit
always @(QA, QB, y)
case (y)
G: begin
s = QA[0] ^ QB[0];
if (QA[0] & QB[0]) Y = H;
else Y = G;
end
H: begin
s = QA[0] ~^ QB[0];
if (~QA[0] &
~QB[0]) Y = G;
else Y = H;
end
default: Y = G;
endcase

// Sequential block
always @(posedge Clock)
if (Reset) y <= G;
else y <= Y;

// Control the shifting process

always @(posedge Clock) Figure 6.49. Verilog code for the serial adder.
if (Reset) Count = 8;
else if (Run) Count = Count - 1;
assign Run = |Count;

endmodule
Week 13 Synchronous Sequential Circuits II Slide24
 1 0 0 0

a7 a0 D3 D2 D1 D0
L
E Counter
L
0 w Q3 Q2 Q1 Q0
1 E

Adder
b7 b0 FSM
Run

L 0 0
0 w
1 E
L
w
E
Clock
Reset
Sum 7 Sum 0

Figure 6.50. Synthesized serial adder.

Week 13 Synchronous Sequential Circuits II Slide25
 Equivalence of states

Two states Si and Sj are said to be equivalent if and only if for

every possible input sequence, the same output sequence will
be produced regardless of whether Si or Sj is the initial state.

Week 13 Synchronous Sequential Circuits II Slide26

 Present Next state Output
state w= 0 w= 1 z

A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0

Figure 6.51. State table for Example 6.6.

Week 13 Synchronous Sequential Circuits II Slide27

 Present Nextstate Output
state w= 0 w= 1 z

A B C 1
B A F 1
C F C 0
F C A 0

Figure 6.52. Minimized state table for Example 6.6.

Week 13 Synchronous Sequential Circuits II Slide28

 Clock

sense N

sense D

(a) Timing diagram

N
sense N D Q D Q

Clock Q Q

(b) Circuit that generates N

Figure 6.53. Signals for the vending machine.
Week 13 Synchronous Sequential Circuits II Slide29
 DN

Reset
DN
DN S1 0 DN

DN DN
D N

D
S4 1 S2 0 S3 0 S7 1
N

D N
DN
S5 1 S6 0 DN DN

N D

S8 1 S9 1

Figure 6.54. State diagram for Example 6.7.

Week 13 Synchronous Sequential Circuits II Slide30
 Present Next state Output
state DN =00 01 10 11 z

S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S6 S7 – 0
S4 S1 – – – 1
S5 S3 – – – 1
S6 S6 S8 S9 – 0
S7 S1 – – – 1
S8 S1 – – – 1
S9 S3 – – – 1

Figure 6.55. State table for Example 6.7.

Week 13 Synchronous Sequential Circuits II Slide31
 Present Next state Output
state DN =00 01 10 11 z

S1 S1 S3 S2 – 0
S2 S2 S4 S5 – 0
S3 S3 S2 S4 – 0
S4 S1 – – – 1
S5 S3 – – – 1

Figure 6.56. Minimized state table for Example 6.7.

Week 13 Synchronous Sequential Circuits II Slide32

 DN

S1 0

N
DN

S3 0
D

DN N DN

D
DN S2 0 S5 1

N
D
S4 1

Figure 6.57. Minimized state diagram for Example 6.7.

Week 13 Synchronous Sequential Circuits II Slide33
 DN 0

S1

N 0 D 1

DN 0

N 1 S3 D 0

N 0 D 1

S2

DN 0
Figure 6.58. Mealy-type FSM for Example 6.7.
Week 13 Synchronous Sequential Circuits II Slide34
 Present Next state Output z
state w= 0 w= 1 w= 0 w= 1
A B C 0 0
B D – 0 –
C F E 0 1
D B G 0 0
E F C 0 1
F E D 0 1
G F – 0 –

Figure 6.59. Incompletely specified state table for Example 6.8.

Week 13 Synchronous Sequential Circuits II Slide35

Reference
Chapter – 6 – S. Brown and Z. Vranesic “Fundamentals of Digital Logic with
Verilog Design”

Week 13 Synchronous Sequential Circuits II Slide36

Further Reading
Chapter 6 : Sections- 6.3, 6.4 S. Brown and Z. Vranesic “Fundamentals of
Digital Logic with Verilog Design”

If you have any questions or concerns, email the Instructor.

Happy Learning!

Week 13 Synchronous Sequential Circuits II Slide37