Lecture 8

Synchronous Sequential Circuits - I

Prabha Sundaravadivel
Assistant Professor
Department of Electrical Engineering
The University of Texas at Tyler
3900 University Blvd. RBN 1008,
Tyler, TX. 75799
Email: [email protected]

Module 8
EENG VLSI 4332, 5335
Week 12

Week 12 Synchronous Sequential Circuits Slide1

 In a combinational circuit, the values of the outputs are
determined solely by the present values of its inputs.

In a sequential circuit, the values of the outputs

depend on the past behavior of the circuit, as
well as the present values of its inputs.

A sequential circuit has states, which in

conjunction with the present values of inputs
determine its behavior.

Week 12 Synchronous Sequential Circuits Slide2

 Sequential circuits can be:

• Synchronous – where flip-flops are used to

implement the states, and a clock signal is used to
control the operation

• Asynchronous – where no clock is used

Week 12 Synchronous Sequential Circuits Slide3

 W Combinational Combinational
Flip-flops circuit Z
circuit Q

Clock

Figure 6.1. The general form of a synchronous sequential circuit.

Week 12 Synchronous Sequential Circuits Slide4

 If the outputs depend only on the present state, the
circuit is said to be of Moore type.

If the outputs depend on both the present state and

the present values of the inputs, the circuit is said
to be of Mealy type.

Week 12 Synchronous Sequential Circuits Slide5

 Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0

Figure 6.2. Sequences of input and output signals.

Week 12 Synchronous Sequential Circuits Slide6

 Reset

w = 1
w = 0 A z = 0 B z = 0

w = 0

w = 0 w = 1

C z = 1

w = 1

Figure 6.3. State diagram of a simple sequential circuit.

Week 12 Synchronous Sequential Circuits Slide7
 Present Next state Output
state w= 0 w= 1 z

A A B 0
B A C 0
C A C 1

Figure 6.4. State table for the sequential circuit in Figure 6.3.
Week 12 Synchronous Sequential Circuits Slide8
 Y1 y1
w
Combinational Combinational z
circuit circuit

Y2 y2

Clock

Figure 6.5. A general sequential circuit with input w, output z,

and two state flip-flops.
Week 12 Synchronous Sequential Circuits Slide9
 The present state variables, y1 and y2, determine the
present state of the circuit.

The next state variables, Y1 and Y2, determine the state

into which the circuit will go after the next active edge
of the clock signal.

Week 12 Synchronous Sequential Circuits Slide10

 Next state
Present
w = 0 w = 1 Output
state
z
y y Y Y Y Y
2 1 2 1 2 1
A 00 00 01 0
B 01 00 10 0
C 10 00 10 1
11 dd dd d

Figure 6.6. State-assigned table for the sequential circuit in Figure 6.4.
Week 12 Synchronous Sequential Circuits Slide11
 y y
2 1
Ignoring don't cares Using don't cares
w 00 01 11 10

0 0 0 d 0
Y = wy y Y = wy y
1 1 2 1 1 2
1 1 0 d 0

y y
2 1
w
00 01 11 10

0 0 0 d 0
Y = wy y + wy y Y = wy + wy
2 1 2 1 2 2 1 2
1 0 1 d 1 = w(y + y )
1 2

y
1
y
2 0 1

0 0 0
z = y y z = y
1 2 2
1 1 d

Figure 6.7. Derivation of logic expressions for the sequential circuit in Figure 6.6.

Week 12 Synchronous Sequential Circuits Slide12

 Figure 6.8. Final implementation of the sequential circuit derived
in Figure 6.7.
Week 12 Synchronous Sequential Circuits Slide13
 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
1
Clock
0

1
w
0

1
y1
0

1
y2
0

1
z
0

Figure 6.9. Timing diagram for the circuit in Figure 6.8.

Week 12 Synchronous Sequential Circuits Slide14
 Design steps

1. Obtain the specification of the desired circuit.

2. Derive a state diagram.
3. Derive the corresponding state table.
4. Reduce the number of states if possible.
5. Decide on the number of state variables.
6. Choose the type of flip-flops to be used.
7. Derive the logic expressions needed to implement
the circuit.

Week 12 Synchronous Sequential Circuits Slide15

 Figure 6.10. System for Example 6.1.
Week 12 Synchronous Sequential Circuits Slide16
 w = 0

A No transfer Reset

w = 1

B R 2 out = 1,R 3 in = 1

w = 0
w = 1
w = 0
w = 1 C R 1 out = 1,R 2 in = 1

w = 0
w = 1

D R 3 out = 1,R 1 in = 1,Done = 1

Figure 6.11. State diagram for Example 6.1.

Week 12 Synchronous Sequential Circuits Slide17
 Present Next state Outputs
state w=0 w=1
A A B 0 0 0 0 0 0 0
B C C 0 0 1 0 0 1 0
C D D 1 0 0 1 0 0 0
D A A 0 1 0 0 1 0 1

Figure 6.12. State table for Example 6.1.

Week 12 Synchronous Sequential Circuits Slide18

 Present Next state
state Outputs

A 00 00 01 0 0 0 0 0 0 0
B 01 10 10 0 0 1 0 0 1 0
C 10 11 11 1 0 0 1 0 0 0
D 11 00 00 0 1 0 0 1 0 1

Figure 6.13. State-assigned table for the sequential circuit in Figure 6.12.

Week 12 Synchronous Sequential Circuits Slide19

 y2 y1
w
0 0 0 1 1 1 1 0

0
1

Y 1 = wy 1 + y 1 y 2
1
1 1

y2 y1
w
00 01 11 10

0 1 1
Y 2 = y1 y2 + y1 y2
1 1 1

Figure 6.14. Derivation of next-state expressions for the

sequential circuit in Figure 6.13.
Week 12 Synchronous Sequential Circuits Slide20
 Figure 6.15. Final implementation of sequential circuit in Figure 6.13.
Week 12 Synchronous Sequential Circuits Slide21
 Next state
Present
state w= 0 w= 1 Output
z
y2 y1 Y 2 Y1 Y2 Y1
A 00 00 01 0
B 01 00 11 0
C 11 00 11 1
10 dd dd d

Figure 6.16. Improved state assignment for the sequential circuit

in Figure 6.4.
Week 12 Synchronous Sequential Circuits Slide22
 Y2 y2
D Q z

Y1 y1
w D Q

Clock Q

Resetn

Figure 6.17. Final circuit for the improved state assignment

in Figure 6.16.
Week 12 Synchronous Sequential Circuits Slide23
 Present Nextstate
state Outputs

A 00 00 01 0 0 0 0 0 0 0
B 01 11 11 0 0 1 0 0 1 0
C 11 10 10 1 0 0 1 0 0 0
D 10 00 00 0 1 0 0 1 0 1

Figure 6.18. Improved state assignment for the sequential

circuit in Figure 6.12.
Week 12 Synchronous Sequential Circuits Slide24
 y2 y1
w 00 01 11 10
0 1
Y 1 = wy 2 + y 1 y 2
1 1 1

y2 y1
w
00 01 11 10
0 1 1
Y 2 = y1
1 1 1

Figure 6.19. Derivation of next-state expressions for the sequential

circuit in Figure 6.18.
Week 12 Synchronous Sequential Circuits Slide25
 module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuit

always @(w, y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
elsey <= Y;

// Define output
assign z = (y = = C);
Figure 6.29. Verilog code for the FSM in Figure 6.3.
endmodule

Week 12 Synchronous Sequential Circuits Slide26

 Interconnection wires
Resetn

Clock

PAL-like block

1
1
0

y1
D Q

1
1
0 z
y2
D Q

(Other macrocells are not shown)

Figure 6.30. Implementation of the FSM of Figure 6.3 in a CPLD.

Week 12 Synchronous Sequential Circuits Slide27

 Resetn

Clock
Gnd
w
7 4 1 44 39

10 36

EPM7032
13
z

16
19 22 25 28

V DD
Figure 6.31. The circuit from Figure 6.30 in a small CPLD.
Week 12 Synchronous Sequential Circuits Slide28
 Figure 6.32. Simulation results for the circuit in Figure 6.30.

Week 12 Synchronous Sequential Circuits Slide29

 module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output reg z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the next state combinational circuit

always @(w, y)
begin
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
z = (y = = C); //Define output
end

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
elsey <= Y;

endmodule Figure 6.33. Second version of code for the FSM in Figure 6.3.

Week 12 Synchronous Sequential Circuits Slide30

 module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;

// Define the sequential block

always @(negedge Resetn, posedge Clock)
if (Resetn = = 0) y <= A;
else
case (y)
A: if (w) y <= B;
else y <= A;
B: if (w) y <= C;
else y <= A;
C: if (w) y <= C;
else y <= A;
default: y <= 2'bxx;
endcase

// Define output
assign z = (y = = C);
Figure 6.34. Third version of code for the FSM in Figure 6.3.
endmodule

Week 12 Synchronous Sequential Circuits Slide31

module control (Clock, Resetn, w, R1in, R1out, R2in, R2out, R3in,
R3out,Done);
input Clock, Resetn, w;
output R1in, R1out, R2in, R2out, R3in, R3out, Done;
reg [2:1] y, Y; // Define the sequential block
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11; always @(negedge Resetn, posedge
Clock)
// Define the next state combinational circuit if (Resetn = = 0) y <= A;
always @(w, y) else y <= Y;
case (y)
A: if (w) Y = B; // Define outputs
else Y = A; assign R2out = (y = = B);
B: Y = C; assign R3in = (y = = B);
C: Y = D; assign R1out = (y = = C);
D: Y = A; assign R2in = (y = = C);
endcase assign R3out = (y = = D);
assign R1in = (y = = D);
assign Done = (y = = D);

endmodule

Figure 6.35. Verilog code for the FSM in Figure 6.11.

Week 12 Synchronous Sequential Circuits Slide32

Reference
Chapter – 6 – S. Brown and Z. Vranesic “Fundamentals of Digital Logic with
Verilog Design”

Week 12 Synchronous Sequential Circuits Slide33

Further Reading
Chapter 6 : Sections- 6.1, 6.2, 6.4 Pg – 333-347, 353- 364, S. Brown and Z.
Vranesic “Fundamentals of Digital Logic with Verilog Design”

If you have any questions or concerns, email the Instructor.

Happy Learning!

Week 12 Synchronous Sequential Circuits Slide34