Digital Electronic Circuits
(EC2L004)
Lecture 9: Combinational Logic – Part II
Multiplexers/Data selectors
• A multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a
single output line.
• The selection of a particular input line is controlled by a set of
selection lines.
• Normally, there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 2
4x1 multiplexer
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 3
Quadruple two-to-one-line multiplexer
• Multiplexer circuits can be combined with common selection
inputs to provide multiple-bit selection logic.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 4
Boolean Function Implementation
• Implement the following function using 8x1 mux and also with
4x1 mux.
F (x, y, z) = ∑(1, 2, 6, 7)
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 5
Boolean Function Implementation
• Implement the following function using 8x1 mux
F (A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
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Boolean Function Implementation: Summary
• Step 1: Complete the truth table from the SOP.
• Step 2: The first n – 1 variables in the table are applied to the
selection inputs of the multiplexer.
• Step 3: For each combination of the selection variables, we
evaluate the output as a function of the last variable.
• Step 4: Apply these values to the data input in proper order.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 7
Demultiplexer
• Multiplexer (MUX)
• Routes one of many inputs to a single
output
• Also called a selector
control
• Demultiplexer (DEMUX)
• Single data input; n control inputs
(“selects”); 2n outputs
• Single input connects to one of 2n
outputs
• “Selects” decide which output is
connected to the input
control
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 8
3x8 Demux
• The input is called an “enable” (G)
0
1
2 3:8 Decoder:
3 Out0 = G • S2' • S1' • S0'
G 3:8 4 Out1 = G • S2' • S1' • S0
Demux 5
Out2 = G • S2' • S1 • S0'
6 Out3 = G • S2' • S1 • S0
7
Out4 = G • S2 • S1' • S0'
S2 S1 S0 Out5 = G • S2 • S1' • S0
Out6 = G • S2 • S1 • S0'
Out7 = G • S2 • S1 • S0
A B C
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 9
Demultiplexers: Implemtation
G Out0
S
Out1 G
Out0
1:2 demux
Out1
1:2 Decoder:
Out0 = G • S'
Out1 = G • S Out2
Out3
2:4 Decoder:
Out0 = G • S1' • S0'
Out1 = G • S1' • S0
Out2 = G • S1 • S0'
2:4 demux
Out3 = G • S1 • S0
S1 S0
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 10
Demultiplexer as logic block
• A n:2n demux can implement any function of n variables
• Use variables as select inputs
• Tie enable input to logic 1
• Sum the appropriate minterms (extra OR gate)
0 A'B'C'
1 A'B'C
2 A'BC'
1 3:8 3 A'BC
Demux 4 AB'C'
5 AB'C
6 ABC'
7 ABC demultiplexer “decodes”
S2 S1 S0 appropriate minterms
from the control signals
A B C
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 11
Demultiplexer as logic block
F1 = A'BC'D + A'B'CD + ABCD
F2 = ABC'D' + ABC
0 A'B'C'D'
F3 = (A'+B'+C'+D') 1 A'B'C'D
2 A'B'CD' F1
3 A'B'CD
4 A'BC'D'
5 A'BC'D
6 A'BCD'
7 A'BCD
Enable = 1 4:16 8 AB'C'D'
Demux 9 F2
AB'C'D
10 AB'CD'
11 AB'CD
12 ABC'D'
13 ABC'D
14 ABCD'
15 ABCD F3
A B C D
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 12
Cascading demultiplexers
• 5:32 demux
0 A'B'C'D'E' 0
1 1
2 2 A'BC'DE'
3:8 3 3:8 3
Demux 4 Demux 4
5 5
6 6
7 7
S2 S1 S0 S2 S1 S0
0
2:4 1
F Demux 2
S1 S0 3
0 0 AB'C'D'E'
1 1
A B 2 2
3:8 3 3:8 3
Demux 4 Demux 4
5 5
6 6
7 ABCDE 7 AB'CDE
S2 S1 S0 S2 S1 S0
C D E C D E
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 13
Decoders
• A decoder is a combinational circuit that converts binary
information from n input lines to an 2n unique output lines.
• Some Applications:
• Microprocessor memory system: selecting different banks of
memory.
• Microprocessor I/O: Selecting different devices.
• Memory: Decoding memory addresses (e.g. in ROM).
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Three-to-Eight Line Decoder
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Three-to-Eight Line Decoder
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2-to-4-line DECODER with Enable
• The decoder is enabled when E = 0. The output whose value
= 0 represents the minterm is selected by inputs A and B.
• The decoder is inactive when E = 1 -> D0 …D3 = 1
• A Decoder with enable input is called a decoder/demultiplexer.
• Demultiplexer receives information from a single line and
directs it to the output lines.
0
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2-to-4-line DECODER with Enable
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 18
4x16 decoder with two 3x8 decoders
• When w = 0, the top decoder is enabled and the bottom is disabled.
• Top decoder generates 8 minterms 0000 to 0111, while the bottom
decoder outputs are 0’s.
• When w = 1, the top decoder is disabled and the bottom is enabled.
• Bottom decoder generates 8 minterms 1000 to 1111, while the top
decoder outputs are 0’s.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 19
Implementation of Full Adder using 3x8 Decoder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 20
Encoders
• An encoder is a digital circuit that performs the inverse
operation of a decoder. An encoder has 2n (or fewer) input
lines and n output lines.
• It is assumed that only one input has a value of 1 at any given
point in time.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 21
Encoders (Contd.)
• The encoder can be implemented with OR gates whose
inputs are determined directly from the truth table.
• Two problems
• What if two inputs are active simultaneously?
• Output with all 0’s generated when all the inputs are 0; but this
same as when D0 is equal to 1.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 22
Priority Encoder
• A priority encoder is an encoder circuit that includes the
priority function. The operation of the priority encoder is such
that if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
• Input D3 has the highest priority.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 23
Priority Encoder (Contd.)
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 24
Priority Encoder (Contd.)
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 25
• Disclaimer: Demultiplexer slides are copied from different open
sources on the internet, and I do not claim the ownership of these
slides.
[30/01/2024, IIT BBS] | [Srinivas Boppu] | [SES] | [EC2L004] 26
