Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
10 views9 pages

DLD Lab Report 3

The document outlines Lab #03 for Digital Logic Design at COMSATS University Islamabad, focusing on Verilog and simulation using Xilinx ISE. The lab objectives include verifying basic logic gates and writing Verilog code for various gates, along with creating test benches for simulation. Additionally, a post-lab task involves writing Verilog code for a given Boolean function using both Gate-Level and Dataflow models.

Uploaded by

rayanalisajid7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
10 views9 pages

DLD Lab Report 3

The document outlines Lab #03 for Digital Logic Design at COMSATS University Islamabad, focusing on Verilog and simulation using Xilinx ISE. The lab objectives include verifying basic logic gates and writing Verilog code for various gates, along with creating test benches for simulation. Additionally, a post-lab task involves writing Verilog code for a given Boolean function using both Gate-Level and Dataflow models.

Uploaded by

rayanalisajid7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

COMSATS UNIVERSITY ISLAMABAD

DIGITAL LOGIC DESIGN- EEE241


LAB #03: Introduction to Verilog and Simulation
using XILINX ISE

NAME RAYAN ALI SAJID

REGISTRATION NUMBER FA24-EEE-041

SECTION EEE-2

INSTRUCTOR NAME Dr. AHMED NASEEM ALVI


Objective
In Lab: Verify all the basic logic gates using the Xilinx ISE simulation tool
and compare the waveforms with the truth tables of the logic gates.
Task 1: Write Verilog code (Gate-Level) for NOT, OR, NOR, NAND, XOR,
and XNOR gates.
Task 2: Write a stimulus/test bench for Task 01 and display the
simulation results.
Task #1
FOR NOT GATE:

TEST BENCH CODE:


FOR OR GATE:

TEST BENCH CODE:

FOR NOR GATE:


TEST BENCH CODE:

FOR NAND GATE:

TEST BENCH CODE:


FOR XOR GATE:

TEST BENCH CODE:

FOR XNOR GATE:


Post Lab
Write a Verilog code for the given Boolean function* (e.g. 𝐹 = 𝑥 + 𝑥𝑦 +
𝑦𝑧 ):
a) Using Gate-Level model (Provide Gate Level diagram and Truth
Table)
b) Using Dataflow model
DIAGRAM:

Verilog code:
TEST BECNH CODE:
Lab Assessment
Pre-Lab /1
In-Lab /5
Post- Data /4 /4 /10
Lab Analysis
Data /4
Presentation
Writing /4
Style
Instructor Signature and
Comments

You might also like